A Novel Concept for High-Speed Time Switch Approaching Memory Read Cycle Limit. - Yousuke Yamamoto; Hiroshi Miyanaga; Yoshiji Kobayashi; Yasukazu Terada; Naoaki Yamanaka (IEEE Trans. Commun., 1986)

High-Speed Time Division Switch for 32-Mbit/s Bearer Rate Signals. - Naoaki Yamanaka; Hiroshi Miyanaga; Yousuke Yamamoto (IEEE J. Sel. Areas Commun., 1987)

A real-time 256×256 point two-dimensional FFT single-chip processor. - Hiroshi Miyanaga; Hironori Yamauchi; Kazuhiro Matsuda (ICASSP, 1991)