An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters. - Masataka Matsui; Hiroshi Momose; Yukihiro Urakawa; Takeo Maeda; Azuma Suzuki; Nobuaki Urakawa; Katsuhiko Sato; Jun'ichi Matsunaga; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1989)

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network. - Kenji Sakaue; Yasuro Shobatake; Masahiko Motoyama; Yoshinari Kumaki; Satoru Takatsuka; Shigeru Tanaka; Hiroyuki Hara; Kouji Matsuda; Shuji Kitaoka; Makoto Noda; Youichiro Niitsu; Masayuki Norishima; et al. (IEEE J. Solid State Circuits, 1991)

0.5- mu m 2 M-transistor BiPNMOS channelless gate array. - Hiroyuki Hara; Takayasu Sakurai; Makoto Noda; Tetsu Nagamatsu; Katsuhiro Seta; Hiroshi Momose; Yoichirou Niitsu; Hiroyuki Miyakawa; Yoshinori Watanabe (IEEE J. Solid State Circuits, 1991)

0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file. - Hiroyuki Hara; Takayasu Sakurai; Tetsu Nagamatsu; Katsuhiro Seta; Hiroshi Momose; Yoichirou Niitsu; Hiroyuki Miyakawa; Kouji Matsuda; Yoshinori Watanabe; Fumihiko Sano; Akihiko Chiba (IEEE J. Solid State Circuits, 1992)

Range-expanding wildlife: modelling the distribution of large mammals in Japan, with management implications. - Masayuki U. Saito; Hiroshi Momose; Satoshi Inoue; Osamu Kurashima; Hiroyuki Matsuda (Int. J. Geogr. Inf. Sci., 2016)

An FPGA Accelerator for Embedded Microcontrollers Implementing a Ternarized Backpropagation Algorithm. - Tatsuya Kaneko; Hiroshi Momose; Tetsuya Asai (ReConFig, 2019)