Error Correction Algorithm for Folding/Interpolation ADC. - Haruo Kobayashi 001; Hiroshi Sakayori; Tsutomu Tobari; Hiroyuki Matsuura (ISCAS, 1995)

ADC standard and testing in Japanese industry. - Haruo Kobayashi 001; Kensuke Kobayashi; Hiroshi Sakayori; Yasuyuki Kimura (Comput. Stand. Interfaces, 2001)

Algorithms for Digital Correction of ADC Nonlinearity. - Haruo Kobayashi 001; Hiroshi Yagi; Takanori Komuro; Hiroshi Sakayori (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A practical BIST circuit for analog portion in deep sub-micron CMOS system LSI. - Takanori Komuro; Naoto Hayasaka; Haruo Kobayashi 001; Hiroshi Sakayori (ISCAS (5), 2005)

A Practical Analog BIST Cooperated with an LSI Tester. - Takanori Komuro; Naoto Hayasaka; Haruo Kobayashi 001; Hiroshi Sakayori (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Total Harmonic Distortion Measurement System of Electronic Devices up to 100 MHz With Remarkable Sensitivity. - Takanori Komuro; Shingo Sobukawa; Hiroshi Sakayori; Masashi Kono; Haruo Kobayashi 001 (IEEE Trans. Instrum. Meas., 2007)