New three-dimensional memory array architecture for future ultrahigh-density DRAM. - Tetsuo Endoh; Katsuhisa Shinmei; Hiroshi Sakuraba; Fujio Masuoka (IEEE J. Solid State Circuits, 1999)

An on-chip 96.5% current efficiency CMOS linear regulator. - Kazuhisa Sunaga; Tetsuo Endoh; Hiroshi Sakuraba; Fujio Masuoka (ASP-DAC, 2001)

An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current. - Tetsuo Endoh; Kazuhisa Sunaga; Hiroshi Sakuraba; Fujio Masuoka (IEEE J. Solid State Circuits, 2001)

0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation. - Akira Tanabe; Masato Umetani; Ikuo Fujiwara; Takayuki Ogura; Kotaro Kataoka; Masao Okihara; Hiroshi Sakuraba; Tetsuo Endoh; Fujio Masuoka (IEEE J. Solid State Circuits, 2001)

Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering. - Yasue Yamamoto; Takeshi Hidaka; Hiroki Nakamura; Hiroshi Sakuraba; Fujio Masuoka (IEICE Trans. Electron., 2006)

Use of Haar wavelet transform based multiple template matching for analyses of speech voice. - Shinji Karasawa; Hiroshi Sakuraba (EATIS, 2007)