Dynamic Instruction Cascading on GALS Microprocessors. - Hiroshi Sasaki 001; Masaaki Kondo; Hiroshi Nakamura (PATMOS, 2005)

An intra-task dvfs technique based on statistical analysis of hardware events. - Hiroshi Sasaki 001; Yoshimichi Ikeda; Masaaki Kondo; Hiroshi Nakamura (Conf. Computing Frontiers, 2007)

Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS. - Masaaki Kondo; Hiroshi Sasaki 001; Hiroshi Nakamura (SIGARCH Comput. Archit. News, 2007)

Power-performance modeling of heterogeneous cluster-based web servers. - Hiroshi Sasaki 001; Takatsugu Oya; Masaaki Kondo; Hiroshi Nakamura (GRID, 2009)

Cooperative shared resource access control for low-power chip multiprocessors. - Noriko Takagi; Hiroshi Sasaki 001; Masaaki Kondo; Hiroshi Nakamura (ISLPED, 2009)

Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping. - Hiroshi Sasaki 001; Masaaki Kondo; Hiroshi Nakamura (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Performance evaluation of 3D stacked multi-core processors with temperature consideration. - Takaaki Hanada; Hiroshi Sasaki 001; Koji Inoue; Kazuaki J. Murakami (3DIC, 2011)

Scalability-based manycore partitioning. - Hiroshi Sasaki 001; Teruo Tanimoto; Koji Inoue; Hiroshi Nakamura (PACT, 2012)

Power and Performance Analysis of GPU-Accelerated Systems. - Yuki Abe 001; Hiroshi Sasaki 001; Martin Peres; Koji Inoue; Kazuaki J. Murakami; Shinpei Kato (HotPower, 2012)

Adaptive Data Compression on 3D Network-on-Chips. - Yuan He 002; Hiroki Matsutani; Hiroshi Sasaki 001; Hiroshi Nakamura (Inf. Media Technol., 2012)

Geyser. - Hiroshi Sasaki 001; Hideharu Amano; Kimiyoshi Usami; Masaaki Kondo; Mitaro Namiki; Hiroshi Nakamura (Handbook of Energy-Aware and Green Computing, 2012)

McRouter: Multicast within a router for high performance network-on-chips. - Yuan He 002; Hiroshi Sasaki 001; Shinobu Miwa; Hiroshi Nakamura (PACT, 2013)

Coordinated power-performance optimization in manycores. - Hiroshi Sasaki 001; Satoshi Imamura; Koji Inoue (PACT, 2013)

SMYLEref: A reference architecture for manycore-processor SoCs. - Masaaki Kondo; Son Truong Nguyen; Tomoya Hirao; Takeshi Soga; Hiroshi Sasaki 001; Koji Inoue (ASP-DAC, 2013)

Line sharing cache: Exploring cache capacity with frequent line value locality. - Keitarou Oka; Hiroshi Sasaki 001; Koji Inoue (ASP-DAC, 2013)

Power and performance of GPU-accelerated systems: A closer look. - Yuki Abe 001; Hiroshi Sasaki 001; Shinpei Kato; Koji Inoue; Masato Edahiro; Martin Peres (IISWC, 2013)

Predict-More Router: A Low Latency NoC Router with More Route Predictions. - Yuan He 002; Hiroshi Sasaki 001; Shinobu Miwa; Hiroshi Nakamura (IPDPS Workshops, 2013)

Power-capped DVFS and thread allocation with ANN models on modern NUMA systems. - Satoshi Imamura; Hiroshi Sasaki 001; Koji Inoue; Dimitrios S. Nikolopoulos (ICCD, 2014)

Power and Performance Characterization and Modeling of GPU-Accelerated Systems. - Yuki Abe 001; Hiroshi Sasaki 001; Shinpei Kato; Koji Inoue; Masato Edahiro; Martin Peres (IPDPS, 2014)

A flexible hardware barrier mechanism for many-core processors. - Takeshi Soga; Hiroshi Sasaki 001; Tomoya Hirao; Masaaki Kondo; Koji Inoue (ASP-DAC, 2015)

Runtime multi-optimizations for energy efficient on-chip interconnections1. - Yuan He 002; Masaaki Kondo; Takashi Nakada; Hiroshi Sasaki 001; Shinobu Miwa; Hiroshi Nakamura (ICCD, 2015)

Characterization and mitigation of power contention across multiprogrammed workloads. - Hiroshi Sasaki 001; Alper Buyuktosunoglu; Augusto Vega; Pradip Bose (IISWC, 2016)

A Scalability Analysis of Many Cores and On-Chip Mesh Networks on the TILE-Gx Platform. - Ye Liu 003; Hiroshi Sasaki 001; Shinpei Kato; Masato Edahiro (MCSoC, 2016)

Power-Efficient Breadth-First Search with DRAM Row Buffer Locality-Aware Address Mapping. - Satoshi Imamura; Yuichiro Yasui; Koji Inoue; Takatsugu Ono; Hiroshi Sasaki 001; Katsuki Fujisawa (HPGDMP@SC, 2016)

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. - Yuan He 002; Masaaki Kondo; Takashi Nakada; Hiroshi Sasaki 001; Shinobu Miwa; Hiroshi Nakamura (IEICE Trans. Inf. Syst., 2016)

Why do programs have heavy tails? - Hiroshi Sasaki 001; Fang-Hsiang Su; Teruo Tanimoto; Simha Sethumadhavan (IISWC, 2017)

Mitigating Power Contention: A Scheduling Based Approach. - Hiroshi Sasaki 001; Alper Buyuktosunoglu; Augusto Vega; Pradip Bose (IEEE Comput. Archit. Lett., 2017)

Heavy Tails in Program Structure. - Hiroshi Sasaki 001; Fang-Hsiang Su; Teruo Tanimoto; Simha Sethumadhavan (IEEE Comput. Archit. Lett., 2017)

Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors. - Teruo Tanimoto; Takatsugu Ono; Koji Inoue; Hiroshi Sasaki 001 (IEEE Comput. Archit. Lett., 2017)

Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs. - Satoshi Imamura; Yuichiro Yasui; Koji Inoue; Takatsugu Ono; Hiroshi Sasaki 001; Katsuki Fujisawa (IEICE Trans. Inf. Syst., 2018)

Advances in Heterogeneous Computing from Hardware to Software (NII Shonan Meeting 2018-11). - Aaron Smith; Chris Fensch; Hiroshi Sasaki 001 (NII Shonan Meet. Rep., 2018)

Practical Byte-Granular Memory Blacklisting using Califorms. - Hiroshi Sasaki 001; Miguel A. Arroyo; M. Tarek Ibn Ziad; Koustubha Bhat; Kanad Sinha; Simha Sethumadhavan (MICRO, 2019)

RAPLET: Demystifying Publish/Subscribe Latency for ROS Applications. - Keisuke Nishimura; Takahiro Ishikawa; Hiroshi Sasaki 001; Shinpei Kato (RTCSA, 2021)

Teapot: Efficiently Uncovering Spectre Gadgets in COTS Binaries. - Fangzheng Lin; Zhongfa Wang; Hiroshi Sasaki 001 (CGO, 2025)