An efficient small signal frequency analysis method of nonlinear circuits with two frequency excitations. - Makiko Okumura; Tsutomu Sugawara; Hiroshi Tanimoto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Realization of a 1-V active filter using a linearization technique employing plurality of emitter-coupled pairs. - Hiroshi Tanimoto; Mikio Koyama; Yoshihiro Yoshida (IEEE J. Solid State Circuits, 1991)

A 1.2- mu m BiCMOS sample-and-hold circuit with a constant-impedance, slew-enhanced sampling gate. - Myles H. Wakayama; Hiroshi Tanimoto; Takahiro Tasai; Yoshihiro Yoshida (IEEE J. Solid State Circuits, 1992)

A 2.5-V active low-pass filter using all-n-p-n Gilbert cells with a 1-Vp-p range. - Mikio Koyama; Tadashi Arai; Hiroshi Tanimoto; Yoshihiro Yoshida (IEEE J. Solid State Circuits, 1993)

A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment. - Shoji Otaka; Takafumi Yamaji; Ryuichi Fujimoto; Chikau Takahashi; Hiroshi Tanimoto (IEEE J. Solid State Circuits, 1996)

An offset-free LPF for π/4-shift QPSK signal generator. - Hiroshi Tanimoto; Tetsuro Itakura; Takashi Ueno; Akira Yasuda; Kazuhiro Oda (IEEE J. Solid State Circuits, 1996)

A time-domain method for numerical noise analysis of oscillators. - Makiko Okumura; Hiroshi Tanimoto (ASP-DAC, 1997)

A 1.9-GHz Si-bipolar variable attenuator for PHS transmitter. - Shoji Otaka; Hiroshi Tanimoto; Shuji Watanabe; Tadahiko Maeda (IEEE J. Solid State Circuits, 1997)

An I/Q active balanced harmonic mixer with IM2 cancelers and a 45° phase shifter. - Takafumi Yamaji; Hiroshi Tanimoto; Hideyuki Kokatsu (IEEE J. Solid State Circuits, 1998)

A third-order ΔΣ modulator using second-order noise-shaping dynamic element matching. - Akira Yasuda; Hiroshi Tanimoto; Tetsuya Iida (IEEE J. Solid State Circuits, 1998)

A 2 Vpp linear input-range fully balanced CMOS transconductor and its application to a 2.5 V 2.5 MHz Gm-C LPF. - Tetsuro Itakura; Takashi Ueno; Hiroshi Tanimoto; Tadashi Arai (CICC, 1999)

A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC. - Tetsuro Itakura; Takashi Ueno; Hiroshi Tanimoto; Akira Yasuda; Ryuichi Fujimoto; Tadashi Arai; Hideyuki Kokatsu (IEEE J. Solid State Circuits, 1999)

A low-power low-noise accurate linear-in-dB variable-gain amplifier with 500-MHz bandwidth. - Shoji Otaka; Gaku Takemura; Hiroshi Tanimoto (IEEE J. Solid State Circuits, 2000)

Nonlinear Analysis of Bipolar Harmonic Mixer for Direct Conversion Receivers. - Hiroshi Tanimoto; Ryuta Ito; Takafumi Yamaji (IEICE Trans. Electron., 2005)

Design Considerations for RC Polyphase Filters with Simultaneously Equal Ripple Both in Stopband and Passband. - Hiroaki Tanabe; Hiroshi Tanimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Transfer Function Preserving Transformations on Equal-Ripple RC Polyphase Filters for Reducing Design Efforts. - Hiroaki Tanabe; Hiroshi Tanimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Very Wideband Active RC Polyphase Filter with Minimum Element Value Spread Using Fully Balanced OTA Based on CMOS Inverters. - Keishi Komoriyama; Makoto Yashiki; Eiichi Yoshida; Hiroshi Tanimoto (IEICE Trans. Electron., 2008)

Design and Implementation of 0.8-V Active RC Polyphase Filter using 0.18-µm CMOS Inverters with Resistive Level Shifter. - Kazuki Yazawa; Hiroshi Tanimoto (ISCAS, 2009)

Design of 1 V Operating Fully Differential OTA Using NMOS Inverters in 0.18 µm CMOS Technology. - Atsushi Tanaka; Hiroshi Tanimoto (IEICE Trans. Electron., 2009)

Cascade synthesis of RC polyphase one-ports. - Tetsuo Nishi; Hiroshi Tanimoto; Shin'ichi Oishi (ECCTD, 2011)

Harmonic Signal Rejection Schemes of Polyphase Downconverters. - Takafumi Yamaji; Hiroshi Tanimoto; Junya Matsuno; Tetsuro Itakura (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Exact Design of RC Polyphase Filters and Related Issues. - Hiroshi Tanimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

VLSI design of an interference canceller for QPSK OFDM-IDMA systems. - Mai Nozaki; Shingo Yoshizawa; Hiroshi Tanimoto (APCCAS, 2014)

Evaluation of diversity combining methods for underwater acoustic OFDM communication. - Ryuta Ishimoto; Shingo Yoshizawa; Hiroshi Tanimoto; Takashi Saito (ISPACS, 2014)

Performance evaluation of antenna diversity with iterative decoding in OFDM-IDMA systems. - Akane Tajima; Shingo Yoshizawa; Hiroshi Tanimoto (DSP, 2015)

A stochastic flash A-to-D converter with dynamic element matching technique. - Toshiki Sugimoto; Hiroshi Tanimoto; Shingo Yoshizawa (ISCIT, 2015)

FPGA implementation of stochastic flash A-to-D converter and its evaluation. - Hisato Takehata; Toshiki Sugimoto; Hiroshi Tanimoto; Shingo Yoshizawa (ISCIT, 2015)

A low power OFDM receiver monitoring subcarrier SNRs in time-varying fading channels. - Shingo Yoshizawa; Hiroshi Tanimoto (ISCIT, 2015)

Experimental evaluation of data selective rake reception for underwater acoustic communication. - Shun Akada; Shingo Yoshizawa; Hiroshi Tanimoto; Takashi Saito (ISPACS, 2015)

VLSI Implementation of an Interference Canceller Using Dual-Frame Processing for OFDM-IDMA Systems. - Shingo Yoshizawa; Mai Nozaki; Hiroshi Tanimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

SC-FDE vs OFDM: Performance comparison in shallow-sea underwater acoustic communication. - Shingo Yoshizawa; Hiroshi Tanimoto; Takashi Saito (ISPACS, 2016)

Power Reduction of Variable Wordlength OFDM Receiver in Time-Varying Fading Channels by Monitoring Subcarrier SNRs. - Shingo Yoshizawa; Daichi Sasaki; Hiroshi Tanimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A simple current reference with low sensitivity to supply voltage and temperature. - Tatsuya Abe 004; Hiroshi Tanimoto; Shingo Yoshizawa (MIXDES, 2017)

Comparator design for linearized statistical flash A-to-D converter. - Toshiki Sugimoto; Hiroshi Tanimoto; Shingo Yoshizawa (MIXDES, 2017)

Data Selective Rake Reception for Underwater Acoustic Communication in Strong Multipath Interference. - Shingo Yoshizawa; Hiroshi Tanimoto; Takashi Saito (J. Electr. Comput. Eng., 2017)

Systematic Construction of Resistor Ladder Network for N-ary DACs. - Manato Hirai; Shuhei Yamamoto; Hirotaka Arai; Anna Kuwana; Hiroshi Tanimoto; Yuji Gendai; Haruo Kobayashi 001 (ASICON, 2019)

Nonlinearity Analysis of Resistive Ladder-Based Current-Steering Digital-to-Analog Converter. - Manato Hirai; Hiroshi Tanimoto; Yuji Gendai; Shuhei Yamamoto; Anna Kuwana; Haruo Kobayashi 001 (ISOCC, 2020)

The Airborne and Satellite Investigation of Asian Air Quality (Asia-Aq): An Opportunity for International Collaboration. - James H. Crawford; Katherine R. Travis; Laura M. Judd; Barry L. Lefer; Jack E. Dibb; Jhoon Kim; Rokjin Park; Gangwoong Lee; Limseok Chang; James Bernard B. Simpas; Maria Obiminda L. Cambaliza; Ronald C. Macatangay; et al. (IGARSS, 2022)

Back to the Analog Neural Network and Linear Circuit Theory. - Haruo Kobayashi 001; Manato Hirai; Kakeru Otomo; Shogo Katayama; Xueyan Bai; Masashi Chiba; Zifei Xu; Dan Yao; Lengkhang Nengvang; Minh Tri Tran 001; Kanji Yoshihiro; Anna Kuwana; et al. (ASICON, 2023)