Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor. - Toru Asano; Joel Silberman; Sang H. Dhong; Osamu Takahashi; Michael White; Scott R. Cottier; Takaaki Nakazato; Atsushi Kawasumi; Hiroshi Yoshihara (IEEE Micro, 2005)

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI. - Osamu Takahashi; Chad Adams; D. Ault; Erwin Behnen; O. Chiang; Scott R. Cottier; Paula K. Coulman; James Culp; Gilles Gervais; M. S. Gray; Y. Itaka; C. J. Johnson; et al. (ISSCC, 2008)

A 4Mb conductive-bridge resistive memory with 2.3GB/s read-throughput and 216MB/s program-throughput. - Wataru Otsuka; Koji Miyata; Makoto Kitagawa; Keiichi Tsutsui; Tomohito Tsushima; Hiroshi Yoshihara; Tomohiro Namise; Yasuhiro Terao; Kentaro Ogata (ISSCC, 2011)

A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology. - Hiroshi Maejima; Kazushige Kanda; Susumu Fujimura; Teruo Takagiwa; Susumu Ozawa; Jumpei Sato; Yoshihiko Shindo; Manabu Sato; Naoaki Kanagawa; Junji Musha; Satoshi Inoue; Katsuaki Sakurai; et al. (ISSCC, 2018)

A Practical Two-Stage Recipe for Mathematical LLMs: Maximizing Accuracy with SFT and Efficiency with Reinforcement Learning. - Hiroshi Yoshihara; Taiki Yamaguchi; Yuichi Inoue (CoRR, 2025)