An example of fault site localization on a 0.18 mum CMOS device with combination of front and backside techniques. - Yoshiteru Yamada; Hirotaka Komoda (Microelectron. Reliab., 2004)

Novel charge neutralization techniques applicable to wide current range of FIB processing in FIB-SEM combined system. - Hirotaka Komoda; Masaaki Yoshida; Yoh Yamamoto; Kouji Iwasaki; Ikuko Nakatani; Heiji Watanabe; Kiyoshi Yasutake (Microelectron. Reliab., 2006)

Sample tilting technique for preventing electrostatic discharge during high-current FIB gas-assisted etching with XeF2. - Hirotaka Komoda; Chie Moritani; Kazutaka Takahashi 002; Heiji Watanabe; Kiyoshi Yasutake (Microelectron. Reliab., 2007)

Decapsulation technique using electrochemical etching for failure analysis of WLCSP n-type Si assembled module devices. - Takuya Naoe; Hirotaka Komoda (Microelectron. Reliab., 2012)

Via high resistance failure analysis of LSI devices induced by multiple factors related to process and design. - Takuya Naoe; Hirotaka Komoda; Tamao Ikeuchi; Kohichi Yokoyama (Microelectron. Reliab., 2012)