Double MAC on a Cell: A 22-nm 8T-SRAM-Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline. - Hiroto Tagata; Takashi Sato 001; Hiromitsu Awano (IEEE Open J. Circuits Syst., 2024)

Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation. - Hiroto Tagata; Takashi Sato 001; Hiromitsu Awano (CoRR, 2025)