Width and Depth of Combinational Logic Circuits. - Hiroto Yasuura (Inf. Process. Lett., 1981)

An Interactive Simulation System for structured logic design - ISS. - Takeshi Sakai; Yoshiyuki Tsuchida; Hiroto Yasuura; Yasushi Ooi; Yoshitsugu Ono; Hiroshi Kano; Shinji Kimura; Shuzo Yajima (DAC, 1982)

Hardware Algorithms and Logic Design Automation. An Overview and Progress Report. - Shuzo Yajima; Hiroto Yasuura (RIMS Symposium on Software Science and Engineering, 1982)

The Parallel Enumeration Sorting Scheme for VLSI. - Hiroto Yasuura; Naofumi Takagi; Shuzo Yajima (IEEE Trans. Computers, 1982)

On Parallel Computational Complexity of Unification. - Hiroto Yasuura (FGCS, 1984)

Hardware Algorithms for VLSI Systems. - Hiroto Yasuura; Shuzo Yajima (VLSI Engineering, 1984)

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. - Naofumi Takagi; Hiroto Yasuura; Shuzo Yajima (IEEE Trans. Computers, 1985)

On high-speed parallel algorithms using redundant coding. - Hiroto Yasuura; Naofumi Takagi; Shuzo Yajima (Syst. Comput. Jpn., 1987)

High-Speed Logic Simulation on Vector Processors. - Nagisa Ishiura; Hiroto Yasuura; Shuzo Yajima (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Locally Computable Coding for Unary Operations. - Hiroto Yasuura (Concurrency: Theory, Language, And Architecture, 1989)

Semantics of a Hardware Design Language for Japanese Standardization. - Hiroto Yasuura; Nagisa Ishiura (DAC, 1989)

NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. - Nagisa Ishiura; Hiroto Yasuura; Shuzo Yajima (DAC, 1990)

Extraction of Functional Information from Combinatorial Circuits. - M. Ohmura; Hiroto Yasuura; Keikichi Tamaru (ICCAD, 1990)

Formal semantics of UDL/I and its applications to CAD/DA tools. - Hiroto Yasuura; Nagisa Ishiura (ICCD, 1990)

Design of data-path module generators from algorithmic representations. - Vasily G. Moshnyaga; Keikichi Tamaru; Hiroto Yasuura (Synthesis for Control Dominated Circuits, 1992)

A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. - Takashi Hashimoto; Kazuaki J. Murakami; Tetsuo Hironaka; Hiroto Yasuura (International Conference on Supercomputing, 1993)

Design Reuse: Fact or Fiction? (Panel). - Nikil D. Dutt; David Agnew; Raul Camposano; Antun Domic; Manfred Wiesel; Hiroto Yasuura (DAC, 1994)

A Proposal for a Co-design Method in Control Systems Using Combination of Models. - Hisao Koizumi; Katsuhiko Seo; Fumio Suzuki; Yoshisuke Ohtsuru; Hiroto Yasuura (IEICE Trans. Inf. Syst., 1995)

Foreword. - Hiroto Yasuura (IEICE Trans. Inf. Syst., 1995)

Optimal Code Placement of Embedded Software for Instruction Caches. - Hiroyuki Tomiyama; Hiroto Yasuura (ED&TC, 1996)

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. - Tohru Ishihara; Hiroto Yasuura (ISLPED, 1996)

Size-Constrained Code Placement for Cache Miss Rate Reduction. - Hiroyuki Tomiyama; Hiroto Yasuura (ISSS, 1996)

On the Computational Power of Binary Decision Diagram with Redundant Variables. - Tetsuya Yamada; Hiroto Yasuura (Formal Methods Syst. Des., 1996)

A HW/SW co-design environment for multi-media equipments development using inverse problem. - Fumio Suzuki; Hisao Koizumi; M. Hiramine; K. Yamamoto; Hiroto Yasuura; K. Okino (CODES, 1997)

Memory-CPU Size Optimization for Embedded System Designs. - Barry Shackleford; Mitsuhiro Yasuda; Etsuko Okushi; Hisao Koizumi; Hiroyuki Tomiyama; Hiroto Yasuura (DAC, 1997)

A High-Performance Hardware Implementation of a Survival-Based Genetic Algorithm. - Barry Shackleford; Etsuko Okushi; Mitsuhiro Yasuda; Hisao Koizumi; Katsuhiko Seo; Takashi Iwamoto; Hiroto Yasuura (ICONIP (1), 1997)

Code placement techniques for cache miss rate reduction. - Hiroyuki Tomiyama; Hiroto Yasuura (ACM Trans. Design Autom. Electr. Syst., 1997)

Power-Pro: Programmable Power Management Architecture. - Tohru Ishihara; Hiroto Yasuura (ASP-DAC, 1998)

Module Selection Using Manufacturing Information. - Hiroyuki Tomiyama; Hiroto Yasuura (ASP-DAC, 1998)

Instruction Scheduling for Power Reduction in Processor-Based System Design. - Hiroyuki Tomiyama; Tohru Ishihara; Akihiko Inoue; Hiroto Yasuura (DATE, 1998)

Voltage scheduling problem for dynamically variable voltage processors. - Tohru Ishihara; Hiroto Yasuura (ISLPED, 1998)

Instruction Encoding Techniques for Area Minimization of Instruction ROM. - Takanori Okuma; Hiroyuki Tomiyama; Akihiko Inoue; Eko Fajar; Hiroto Yasuura (ISSS, 1998)

Statistical Performance-Driven Module Binding in High-Level Synthesis. - Hiroyuki Tomiyama; Akihiko Inoue; Hiroto Yasuura (ISSS, 1998)

A novel test methodology for core-based system LSIs and a testing time minimization problem. - Makoto Sugihara; Hiroshi Date; Hiroto Yasuura (ITC, 1998)

Embedded System Design Using Soft-Core Processor and Valen-C. - Hiroto Yasuura; Hiroyuki Tomiyama; Akihiko Inoue; Eko Fajar (J. Inf. Sci. Eng., 1998)

Real-Time Task Scheduling for a Variable Voltage Processor. - Takanori Okuma; Tohru Ishihara; Hiroto Yasuura (ISSS, 1999)

One language or more?: how can we design an SoC at a system level? - Masaharu Imai; Gary Smith 001; Steven Schulz; Karen Bartleson; Daniel Gajski; Wolfgang Rosenstiel; Peter Flake; Hiroto Yasuura (ASP-DAC, 2000)

A Bus Delay Reduction Technique Considering Crosstalk. - Kei Hirose; Hiroto Yasuura (DATE, 2000)

A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. - Tohru Ishihara; Hiroto Yasuura (DATE, 2000)

Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. - Makoto Sugihara; Hiroto Yasuura; Hiroshi Date (DATE, 2000)

An FPGA-based genetic algorithm machine (poster abstract). - Barry Shackleford; Etsuko Okushi; Mitsuhiro Yasuda; Hisao Koizumi; Katsuhiko Seo; Takashi Iwamoto; Hiroto Yasuura (FPGA, 2000)

Variable size analysis and validation of computation quality. - Hajime Yamashita; Hiroto Yasuura; Eko Fajar; Yun Cao (HLDVT, 2000)

Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-Offs. - Victor M. Goulart Ferreira; Hiroto Yasuura (SBCCI, 2000)

Flexible System LSI for Embedded Systems and Its Optimization Techniques. - Akihiko Inoue; Tohru Ishihara; Hiroto Yasuura (Des. Autom. Embed. Syst., 2000)

Editorial. - Hiroto Yasuura (Des. Autom. Embed. Syst., 2000)

A system-level energy minimization approach using datapath width optimization. - Yun Cao; Hiroto Yasuura (ISLPED, 2001)

Software Energy Reduction Techniques for Variable-Voltage Processors. - Takanori Okuma; Hiroto Yasuura; Tohru Ishihara (IEEE Des. Test Comput., 2001)

A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine. - Barry Shackleford; Greg Snider; Richard J. Carter; Etsuko Okushi; Mitsuhiro Yasuda; Katsuhiko Seo; Hiroto Yasuura (Genet. Program. Evolvable Mach., 2001)

A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA. - Shoji Goto; Takashi Yamada; Norihisa Takayarna; Yoshifumi Matsushita; Yasoo Harada; Hiroto Yasuura (DSD, 2002)

A low-power digital matched filter for spread-spectrum systems. - Shoji Goto; Takashi Yamada; Norihisa Takayama; Yoshifumi Matsushita; Yasoo Harada; Hiroto Yasuura (ISLPED, 2002)

Reducing access energy of on-chip data memory considering active data bitwidth. - Takanori Okuma; Yun Cao; Masanori Muroyama; Hiroto Yasuura (ISLPED, 2002)

Power analysis techniques for SoC with improved wiring models. - Takeshi Sakamoto; Takashi Yamada; Mamoru Mukuno; Yoshifumi Matsushita; Yasoo Harada; Hiroto Yasuura (ISLPED, 2002)

An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems. - Hiroto Yasuura; Yun Cao; Mohammad Mesbah Uddin (ISSS, 2002)

Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. - Hiroto Yasuura; Hiroyuki Tomiyama; Takanori Okuma; Yun Cao (ISSS, 2002)

Special Session: Security on SoC. - Hiroto Yasuura; Naofumi Takagi; Srivaths Ravi 001; Michael Torla; Catherine H. Gebotys (ISSS, 2002)

A Power Minimization Technique for Arithmetic Circuits by Cell Selection. - Masanori Muroyama; Tohru Ishihara; Akihiko Hyodo; Hiroto Yasuura (ASP-DAC/VLSI Design, 2002)

Optimization of Test Accesses with a Combined BIST and External Test Scheme. - Makoto Sugihara; Hiroto Yasuura (ASP-DAC/VLSI Design, 2002)

Quality-Driven Design for Video Applications. - Yun Cao; Hiroto Yasuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Quality-driven design by bitwidth optimization for video applications. - Yun Cao; Hiroto Yasuura (ASP-DAC, 2003)

Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid. - Atsushi Sakai; Takashi Yamada; Yoshifumi Matsushita; Hiroto Yasuura (ASP-DAC, 2003)

A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits. - Masanori Muroyama; Akihiko Hyodo; Takanori Okuma; Hiroto Yasuura (DSD, 2003)

Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies. - Hiroto Yasuura (DSD, 2003)

Routing methodology for minimizing 1nterconnect energy dissipation. - Atsushi Sakai; Takashi Yamada; Yoshifumi Matsushita; Hiroto Yasuura (ACM Great Lakes Symposium on VLSI, 2003)

Leakage Power Reduction for Battery-Operated Portable Systems. - Yun Cao; Hiroto Yasuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Variable Pipeline Depth Processor for Energy Efficient Systems. - Akihiko Hyodo; Masanori Muroyama; Hiroto Yasuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Pre-Route Power Analysis Techniques for SoC. - Takashi Yamada; Takeshi Sakamoto; Shinji Furuichi; Mamoru Mukuno; Yoshifumi Matsushita; Hiroto Yasuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Routing Methodology for Minimizing Crosstalk in SoC. - Takashi Yamada; Atsushi Sakai; Yoshifumi Matsushita; Hiroto Yasuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Reduction of coupling effects by optimizing the 3-D configuration of the routing grid. - Atsushi Sakai; Takashi Yamada; Yoshifumi Matsushita; Hiroto Yasuura (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Digitally Named World: Challenges for New Social Infrastructures. - Hiroto Yasuura (ISQED, 2004)

An RFID-based multi-service system for supporting conference events. - Takahiro Watanabe; Sozo Inoue; Hiroto Yasuura; Jun Sasaki; Yasushi Aoki; Kazumi Akimoto (AMT, 2005)

A variation-aware low-power coding methodology for tightly coupled buses. - Masanori Muroyama; Kosuke Tarumi; Koji Makiyama; Hiroto Yasuura (ASP-DAC, 2005)

Toward Unlinkable ID Management for Multi-Service Environments. - Yasunobu Nohara; Sozo Inoue; Hiroto Yasuura (PerCom Workshops, 2005)

Quantitative evaluation of unlinkable ID matching schemes. - Yasunobu Nohara; Sozo Inoue; Kensuke Baba; Hiroto Yasuura (WPES, 2005)

Bitwidth Optimization for Low Power Digital FIR Filter Design. - Kosuke Tarumi; Akihiko Hyodo; Masanori Muroyama; Hiroto Yasuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Special Section on Papers Selected from AP-ASIC 2004. - Hiroto Yasuura; Shoji Kawahito (IEICE Trans. Electron., 2005)

Systematic Error Detection for RFID Reliability. - Sozo Inoue; Hiroto Yasuura; Daisuke Hagiwara (ARES, 2006)

An Energy Characterization Framework for Software-Based Embedded Systems. - Donghoon Lee; Tohru Ishihara; Masanori Muroyama; Hiroto Yasuura; Farzan Fallah (ESTIMedia, 2006)

On Authentication between Human and Computer. - Takahiro Watanabe; Yasunobu Nohara; Kensuke Baba; Sozo Inoue; Hiroto Yasuura (PerCom Workshops, 2006)

Unlinkable Identification for Large-scale RFID Systems. - Yasunobu Nohara; Toru Nakamura; Kensuke Baba; Sozo Inoue; Hiroto Yasuura (Inf. Media Technol., 2006)

A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. - Maziar Goudarzi; Tohru Ishihara; Hiroto Yasuura (ASP-DAC, 2007)

Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. - Yuriko Ishitobi; Tohru Ishihara; Hiroto Yasuura (ESTIMedia, 2007)

A Door Access Control System with Mobile Phones. - Tomomi Yamasaki; Toru Nakamura; Kensuke Baba; Hiroto Yasuura (PWC, 2007)

Unlinkability and Real World Constraints in RFID Systems. - Yasunobu Nohara; Sozo Inoue; Hiroto Yasuura (PerCom Workshops, 2007)

A low complexity and energy efficient dynamic channel allocation algorithm for multiuser OFDM. - Adil El Bourichi; Hiroto Yasuura (WTS, 2007)

A Secure High-Speed Identification Scheme for RFID Using Bloom Filters. - Yasunobu Nohara; Sozo Inoue; Hiroto Yasuura (ARES, 2008)

Simultaneous optimization of memory configuration and code allocation for low power embedded systems. - Tadayuki Matsumura; Tohru Ishihara; Hiroto Yasuura (ACM Great Lakes Symposium on VLSI, 2008)

A Framework of Authentic Post-Issuance Program Modification for Multi-Application Smart Cards. - Mohammad Mesbah Uddin; Salahuddin Muhammad Salim Zabir; Yasunobu Nohara; Hiroto Yasuura (ICWN, 2008)

Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. - Masanori Muroyama; Tohru Ishihara; Hiroto Yasuura (PATMOS, 2008)

A Note on Biometrics-based Authentication with Portable Device. - Shinsuke Ohtsuka; Satoshi Kawamoto; Shigeru Takano; Kensuke Baba; Hiroto Yasuura (SECRYPT, 2008)

A Multi-Application Smart Card System with Authentic Post-Issuance Program Modification. - Mohammad Mesbah Uddin; Yasunobu Nohara; Daisuke Ikeda; Hiroto Yasuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation. - Maziar Goudarzi; Tohru Ishihara; Hiroto Yasuura (Microelectron. J., 2008)

Dependable VLSI: device, design and architecture: how should they cooperate? - Shuichi Sakai; Hidetoshi Onodera; Hiroto Yasuura; James C. Hoe (ASP-DAC, 2009)

Large Scale Business-academia Collaboration in Master Education Course. - Noriaki Sakamoto; Mitsuaki Fukase; Tsunenori Mine; Shigeru Kusakabe; Tsuneo Nakanishi; Yoichi Omori; Mohammad Mesbah Uddin; Keijiro Araki; Akira Fukuda; Hiroto Yasuura; Teruaki Kitasuka (CSEDU (2), 2009)

Modeling Costs of Access Control with Various Key Management Systems. - Tomomi Yamasaki; Shunsuke Inenaga; Daisuke Ikeda; Hiroto Yasuura (PDPTA, 2009)

Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment. - Yuji Kunitake; Kazuhiro Mima; Toshinori Sato; Hiroto Yasuura (IEICE Trans. Electron., 2009)

An Optimization Technique for Low-Energy Embedded Memory Systems. - Tadayuki Matsumura; Tohru Ishihara; Hiroto Yasuura (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion. - Seiichiro Yamaguchi; Yuriko Ishitobi; Tohru Ishihara; Hiroto Yasuura (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

An Information Platform for Low-Literate Villagers. - Ashir Ahmed; Lutfe Kabir; Hiroto Yasuura (AINA, 2010)

An Identifiable Yet Unlinkable Authentication System with Smart Cards for Multiple Services. - Toru Nakamura; Shunsuke Inenaga; Daisuke Ikeda; Kensuke Baba; Hiroto Yasuura (ICCSA (4), 2010)

Signal probability control for relieving NBTI in SRAM cells. - Yuji Kunitake; Toshinori Sato; Hiroto Yasuura (ISQED, 2010)

A Replacement Strategy for Canary Flip-Flops. - Yuji Kunitake; Toshinori Sato; Hiroto Yasuura (PRDC, 2010)

An RTOS in hardware for energy efficient software-based TCP/IP processing. - Naotaka Maruyama; Tohru Ishihara; Hiroto Yasuura (SASP, 2010)

Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories. - Yuriko Ishitobi; Tohru Ishihara; Hiroto Yasuura (J. Signal Process. Syst., 2010)

An Anonymous Authentication Protocol with Single-database PIR. - Toru Nakamura; Shunsuke Inenaga; Kensuke Baba; Daisuke Ikeda; Hiroto Yasuura (AISC, 2011)

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. - Shusuke Yoshimoto; Takuro Amashita; D. Kozuwa; Taiga Takata; Masayoshi Yoshimura; Yusuke Matsunaga; Hiroto Yasuura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2011)

Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI. - Yuji Kunitake; Toshinori Sato; Hiroto Yasuura (IEICE Trans. Electron., 2011)

Towards Modeling Stored-value Electronic Money Systems. - Shunsuke Inenaga; Kenichirou Oyama; Hiroto Yasuura (Inf. Media Technol., 2011)

Password Based Anonymous Authentication with Private Information Retrieval. - Toru Nakamura; Shunsuke Inenaga; Daisuke Ikeda; Kensuke Baba; Hiroto Yasuura (J. Digit. Inf. Manag., 2011)

WiP Abstract: Estimation of Electric Power Consumption of Individuals by Observing People's Activity. - Atsushi Shimada 001; Shigeru Takano; Shigeaki Tagashira; Rin-Ichiro Taniguchi; Hiroto Yasuura (ICCPS, 2012)

Neutron-induced soft error rate estimation for SRAM using PHITS. - Shusuke Yoshimoto; Takuro Amashita; Masayoshi Yoshimura; Yusuke Matsunaga; Hiroto Yasuura; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2012)

Guidelines for mitigating NBTI degradation in on-chip memories. - Yuji Kunitake; Toshinori Sato; Hiroto Yasuura; Takanori Hayashida (ISCIT, 2012)

A Selective Replacement Method for Timing-Error-Predicting flip-Flops. - Yuji Kunitake; Toshinori Sato; Hiroto Yasuura; Takanori Hayashida (J. Circuits Syst. Comput., 2012)

ASP-DAC 2017 keynote speech I-3: Design of society: Beyond digital system design. - Hiroto Yasuura (ASP-DAC, 2017)