A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond. - Tadato Yamagata; Hirotoshi Sato; Kore-aki Fujita; Yasumasa Nishimura; Kenji Anami (IEEE J. Solid State Circuits, 1996)

A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell. - Hirotoshi Sato; Hideaki Nagaoka; Hiroaki Honda; Yukio Maki; Tomohisa Wada; Yutaka Arita; Kazuhito Tsutsumi; Makoto Taniguchi; Michihiro Yamada (IEEE J. Solid State Circuits, 1998)

A 500-MHz pipelined burst SRAM with improved SER immunity. - Hirotoshi Sato; Tomohisa Wada; Shigeki Ohbayashi; Kunihiko Kozaru; Yasuyuki Okamoto; Yoshiko Higashide; Tadayuki Shimizu; Yukio Maki; Rui Morimoto; Hisakazu Otoi; Tsuyoshi Koga; Hiroki Honda; et al. (IEEE J. Solid State Circuits, 1999)

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. - Shinji Tanaka; Yuichiro Ishii; Makoto Yabuuchi; Toshiaki Sano; Koji Tanaka; Yasumasa Tsukamoto; Koji Nii; Hirotoshi Sato (VLSIC, 2014)

Application of tablet devices in a chemical laboratory at college of technology. - Hirotoshi Sato; Kozo Fukumoto; Aiko Oshio (SII, 2016)

Application of tablet devices with digitizer pens in a chemical presentation course at college of technology. - Hirotoshi Sato; Kozo Fukumoto; Aiko Oshio (SII, 2017)