Data-dependent logic swing internal bus architecture for ultralow-power LSI's. - Mitsuru Hiraki; Hirotsugu Kojima; Hitoshi Misawa; Takashi Akazawa; Yuji Hatano (IEEE J. Solid State Circuits, 1995)

Half-swing clocking scheme for 75% power saving in clocking circuitry. - Hirotsugu Kojima; Satoshi Tanaka; Katsuro Sasaki (IEEE J. Solid State Circuits, 1995)

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. - Mitsuru Hiraki; Raminder Singh Bajwa; Hirotsugu Kojima; Douglas J. Gorny; Ken-ichi Nitta; Avadhani Shridhar; Katsuro Sasaki; Koichi Seki (ISLPED, 1996)

Interlaced accumulation programming for low power DSP. - Hirotsugu Kojima; Avadhani Shridhar (ISLPED, 1996)

Instruction buffering to reduce power in processors for signal processing. - Raminder Singh Bajwa; Mitsuru Hiraki; Hirotsugu Kojima; Douglas J. Gorny; Ken-ichi Nitta; Avadhani Shridhar; Koichi Seki; Katsuro Sasaki (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Software wave receiver for the SS-520-2 rocket experiment. - Kozo Hashimoto; Hironori Iwai; Yoshikatsu Ueda; Hirotsugu Kojima; Hiroshi Matsumoto (IEEE Trans. Geosci. Remote. Sens., 2003)

A Compact Loop Antenna System for Monitoring Local Electromagnetic Environments in Geospace. - Satoshi Yagitani; Mitsunori Ozaki; Hirotsugu Kojima (IEICE Trans. Commun., 2011)