Energy-efficient high-level synthesis for HDR architectures with clock gating. - Hiroyuki Akasaka; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2012)

Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. - Hiroyuki Akasaka; Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. - Hiroyuki Akasaka; Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2014)