SoC for car navigation systems with a 53.3 GOPS image recognition engine. - Hideaki Kido; Shoji Muramatsu; Yasuhiko Hoshi; Hiroyuki Hamasaki; Atsushi Nakamura; Akihiro Yamamoto (Hot Chips Symposium, 2009)

SOC for car navigation system with a 55.3GOPS image recognition engine. - Hiroyuki Hamasaki; Yasuhiko Hoshi; Atsushi Nakamura; Akihiro Yamamoto; Hideaki Kido; Shoji Muramatsu (ASP-DAC, 2010)

4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control. - Katsushige Matsubara; Hanno Lieske; Motoki Kimura; Atsushi Nakamura; Manabu Koike; Kazuaki Terashima; Shun Morikawa; Yoshihiko Hotta; Takahiro Irita; Seiji Mochizuki; Hiroyuki Hamasaki; Tatsuya Kamei (ISSCC, 2021)

A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control. - Katsushige Matsubara; Hanno Lieske; Motoki Kimura; Atsushi Nakamura; Manabu Koike; Shun Morikawa; Yoshihiko Hotta; Takahiro Irita; Seiji Mochizuki; Hiroyuki Hamasaki; Tatsuya Kamei (IEEE J. Solid State Circuits, 2022)

A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power. - Kenichi Shimada; Keiichiro Sano; Kazuki Fukuoka; Hiroshi Morita; Masayuki Daito; Tatsuya Kamei; Hiroyuki Hamasaki; Yasuhisa Shimazaki (ISSCC, 2023)