A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network. - Kenji Sakaue; Yasuro Shobatake; Masahiko Motoyama; Yoshinari Kumaki; Satoru Takatsuka; Shigeru Tanaka; Hiroyuki Hara; Kouji Matsuda; Shuji Kitaoka; Makoto Noda; Youichiro Niitsu; Masayuki Norishima; et al. (IEEE J. Solid State Circuits, 1991)

0.5- mu m 2 M-transistor BiPNMOS channelless gate array. - Hiroyuki Hara; Takayasu Sakurai; Makoto Noda; Tetsu Nagamatsu; Katsuhiro Seta; Hiroshi Momose; Yoichirou Niitsu; Hiroyuki Miyakawa; Yoshinori Watanabe (IEEE J. Solid State Circuits, 1991)

0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file. - Hiroyuki Hara; Takayasu Sakurai; Tetsu Nagamatsu; Katsuhiro Seta; Hiroshi Momose; Yoichirou Niitsu; Hiroyuki Miyakawa; Kouji Matsuda; Yoshinori Watanabe; Fumihiko Sano; Akihiko Chiba (IEEE J. Solid State Circuits, 1992)

A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme. - Masataka Matsui; Hiroyuki Hara; Yoshiharu Uetani; Lee-Sup Kim; Tetsu Nagamatsu; Yoshinori Watanabe; Akihiko Chiba; Kouji Matsuda; Takayasu Sakurai (IEEE J. Solid State Circuits, 1994)

A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications. - Akilesh Parameswar; Hiroyuki Hara; Takayasu Sakurai (IEEE J. Solid State Circuits, 1996)

Wireless and IP integrated system architectures for broadband mobile multimedia services. - Masahiro Umehira; Masamitsu Nakura; Makoto Umeuchi; Junichi Murayama; Takaaki Murai; Hiroyuki Hara (WCNC, 1999)

A bitline leakage compensation scheme for low-voltage SRAMs. - Ken-ichi Agawa; Hiroyuki Hara; Toshinari Takayanagi; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2001)

Low temperature polycrystalline silicon TFT fingerprint sensor with integrated comparator circuit. - Hiroyuki Hara; Mikio Sakurai; Mitsutoshi Miyasaka; Simon W. B. Tam; Satoshi Inoue; Tatsuya Shimoda (ESSCIRC, 2004)

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. - Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Chen Kong Teh; Takayoshi Shimazawa; Naoyuki Kawabe; Takeshi Kitahara; Yu Kikuchi; Tsuyoshi Nishikawa; Makoto Takahashi; Yukihito Oowaki (CICC, 2005)

Classification of Driving Methods for TFT-OLEDs and Novel Proposal Using Time Ratio Grayscale and Current Uniformization. - Mutsumi Kimura; Yuji Hara; Hiroyuki Hara; Tomoyuki Okuyama; Satoshi Inoue; Tatsuya Shimoda (IEICE Trans. Electron., 2005)

Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems. - Takeshi Kitahara; Hiroyuki Hara; Shinichiro Shiratake; Yoshiki Tsukiboshi; Tomoyuki Yoda; Tetsuaki Utsumi; Fumihiro Minami (ASP-DAC, 2006)

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. - Toshihide Fujiyoshi; Shinichiro Shiratake; Shuou Nomura; Tsuyoshi Nishikawa; Yoshiyuki Kitasho; Hideho Arakida; Yuji Okuda; Yoshiro Tsuboi; Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Fumitoshi Hatori; et al. (IEEE J. Solid State Circuits, 2006)

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems. - Chen Kong Teh; Mototsugu Hamada; Tetsuya Fujita; Hiroyuki Hara; N. Ikumi; Yukihito Oowaki (IEEE Trans. Very Large Scale Integr. Syst., 2006)

An automated runtime power-gating scheme. - Mototsugu Hamada; Takeshi Kitahara; Naoyuki Kawabe; Hironori Sato; Tsuyoshi Nishikawa; Takayoshi Shimazawa; Takahiro Yamashita; Hiroyuki Hara; Yukihito Oowaki (ICCD, 2007)

Pulse-Width Modulation with Current Uniformization for TFT-OLEDs. - Mutsumi Kimura; Shigeki Sawamura; Masakazu Kato; Yuji Hara; Daisuke Suzuki; Hiroyuki Hara; Satoshi Inoue (IEICE Trans. Electron., 2007)

A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design. - Fumihiko Tachibana; Hironori Sato; Takahiro Yamashita; Hiroyuki Hara; Takeshi Kitahara; Shuou Nomura; Fumiyuki Yamane; Yoshiro Tsuboi; Keiko Seki; Shuuji Matsumoto; Yoshinori Watanabe; Mototsugu Hamada (CICC, 2008)

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. - Shuou Nomura; Fumihiko Tachibana; Tetsuya Fujita; Chen Kong Teh; Hiroyuki Usui; Fumiyuki Yamane; Yukimasa Miyamoto; Chaiyasit Kumtornkittikul; Hiroyuki Hara; Takahiro Yamashita; Jun Tanabe; Masaru Uchiyama; et al. (ISSCC, 2008)

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. - Yu Kikuchi; Makoto Takahashi; Tomohisa Maeda; Hiroyuki Hara; Hideho Arakida; Hideaki Yamamoto; Yousuke Hagiwara; Tetsuya Fujita; Manabu Watanabe; Takayoshi Shimazawa; Yasuo Ohara; Takashi Miyamori; et al. (ISSCC, 2010)

A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access. - Keiichi Kushida; Osamu Hirabayashi; Fumihiko Tachibana; Hiroyuki Hara; Atsushi Kawasumi; Azuma Suzuki; Yasuhisa Takeyama; Yuki Fujimura; Yusuke Niki; Miyako Shizuno; Shinichi Sasaki; Tomoaki Yabe (A-SSCC, 2011)

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications. - Daisuke Taki; Tatsuo Shiozawa; Kuniaki Ito; Youichiro Shiba; Kouji Horisaki; Hirotsugu Kajihara; Toshiyuki Yamagishi; Masahiro Sekiya; Akira Yamaga; Tetsuya Fujita; Hiroyuki Hara; Masanori Kuwahara; et al. (COOL Chips, 2011)

A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS. - Chen Kong Teh; Tetsuya Fujita; Hiroyuki Hara; Mototsugu Hamada (ISSCC, 2011)

A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. - Yu Kikuchi; Makoto Takahashi; Tomohisa Maeda; Masatoshi Fukuda; Yasuhiro Koshio; Hiroyuki Hara; Hideho Arakida; Hideaki Yamamoto; Yousuke Hagiwara; Tetsuya Fujita; Manabu Watanabe; Hirokazu Ezawa; et al. (IEEE J. Solid State Circuits, 2011)

An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation. - Toshiyuki Yamagishi; Tatsuo Shiozawa; Koji Horisaki; Hiroyuki Hara; Yasuo Unekawa (COOL Chips, 2012)

A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation. - Toshiyuki Yamagishi; Tatsuo Shiozawa; Koji Horisaki; Hiroyuki Hara; Yasuo Unekawa (IEICE Trans. Electron., 2013)

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. - Hiroki Noguchi; Kazutaka Ikegami; Keiichi Kushida; Keiko Abe; Shogo Itai; Satoshi Takaya; Naoharu Shimomura; Junichi Ito; Atsushi Kawasumi; Hiroyuki Hara; Shinobu Fujita (ISSCC, 2015)

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. - Hiroki Noguchi; Kazutaka Ikegami; Satoshi Takaya; Eishi Arima; Keiichi Kushida; Atsushi Kawasumi; Hiroyuki Hara; Keiko Abe; Naoharu Shimomura; Junichi Ito; Shinobu Fujita; Takashi Nakada; et al. (ISSCC, 2016)