A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology. - Junji Mori; Masato Nagamatsu; Masashi Hirano; Shigeru Tanaka; Makoto Noda; Yoshiaki Toyoshima; Kazuhiro Hashimoto; Hiroyuki Hayashida; Kenji Maeguchi (IEEE J. Solid State Circuits, 1991)

Yugi Kyoshitsu: the play. - Hiroyuki Hayashida (SIGGRAPH Visual Proceedings, 1996)