A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor. - Kazumasa Suzuki; Masakazu Yamashina; Takashi Nakayama; Masanori Izumikawa; Masahiro Nomura; Hiroyuki Igura; Hideki Heiuchi; Junichi Goto; Toshiaki Inoue; Youichi Koseki; Hitoshi Abiko; Kazuhiro Okabe; et al. (IEEE J. Solid State Circuits, 1994)

A GHz MOS adaptive pipeline technique using MOS current-mode logic. - Masayuki Mizuno; Masakazu Yamashina; Koichiro Furuta; Hiroyuki Igura; Hitoshi Abiko; Kazuhiro Okabe; Atsuki Ono; Hachiro Yamada (IEEE J. Solid State Circuits, 1996)

A 0.25-μm CMOS 0.9-V 100-MHz DSP core. - Masanori Izumikawa; Hiroyuki Igura; Hitoshi Wakabayashi; Ken Nakajima; Tohru Mogami; Tadahiko Horiuchi; Masakazu Yamashina (IEEE J. Solid State Circuits, 1997)

An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing. - Hiroyuki Igura; Yukihiro Naito; Kenya Kazama; Ichiro Kuroda; Masato Motomura; Masakazu Yamashina (IEEE J. Solid State Circuits, 1998)

A low-power W-CDMA demodulator using specially-designed micro-DSPs. - Hiroyuki Igura; Masaru Hirata; Junya Yamada; Masakazu Yamashina; Shigeru Ono (CICC, 2002)

Scalable bus interface for HSDPA co-processor extension. - Toshiki Takeuchi; Hiroyuki Igura; Takeshi Hashimoto; Soichi Tsumura; Naoki Nishi (CICC, 2005)

Stream-access-oriented baseband signal processors for SDR. - Toshiki Takeuchi; Hiroyuki Igura; Masao Ikekawa (ISCAS, 2012)