A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. - Hiroyuki Iwata; Tomokazu Yoneda; Satoshi Ohtake; Hideo Fujiwara (Asian Test Symposium, 2005)

A DFT Method for Time Expansion Model at Register Transfer Level. - Hiroyuki Iwata; Tomokazu Yoneda; Hideo Fujiwara (DAC, 2007)

A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. - Hideo Fujiwara; Hiroyuki Iwata; Tomokazu Yoneda; Chia Yee Ooi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Low Power Decompressor and PRPG with Constant Value Broadcast. - Michal Filipek; Yoshiaki Fukui; Hiroyuki Iwata; Grzegorz Mrugalski; Janusz Rajski; Masahiro Takakura; Jerzy Tyszer (Asian Test Symposium, 2011)

An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms. - Hiroyuki Iwata; Yoichi Maeda; Jun Matsushima; Masahiro Takakura (Asian Test Symposium, 2012)

Multi-configuration Scan Structure for Various Purposes. - Hiroyuki Iwata; Jun Matsushima (ATS, 2016)

Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation. - Senling Wang; Hanan T. Al-Awadhi; Soh Hamada; Yoshinobu Higami; Hiroshi Takahashi; Hiroyuki Iwata; Jun Matsushima (ATS, 2016)

A multichannel-near-infrared-spectroscopy-triggered robotic hand rehabilitation system for stroke patients. - Jongseung Lee; Nobutaka Mukae; Jumpei Arata; Hiroyuki Iwata; Keiji Iramina; Koji Iihara; Makoto Hashizume (ICORR, 2017)

Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST. - Senling Wang; Tomoki Aono; Yoshinobu Higami; Hiroshi Takahashi; Hiroyuki Iwata; Yoichi Maeda; Jun Matsushima (ATS, 2018)

Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262. - Senling Wang; Yoshinobu Higami; Hiroshi Takahashi; Hiroyuki Iwata; Yoichi Maeda; Jun Matsushima (ETS, 2018)

Automotive Functional Safety Assurance by POST with Sequential Observation. - Senling Wang; Yoshinobu Higami; Hiroshi Takahashi; Hiroyuki Iwata; Jun Matsushima (IEEE Des. Test, 2018)

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST. - Hanan T. Al-Awadhi; Tomoki Aono; Senling Wang; Yoshinobu Higami; Hiroshi Takahashi; Hiroyuki Iwata; Yoichi Maeda; Jun Matsushima (IEICE Trans. Inf. Syst., 2020)

A Power Reduction Method for Scan Testing in Ultra-Low Power Designs. - Hiroyuki Iwata; Yoichi Maeda; Jun Matsushima (ATS, 2021)

A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy. - Hiroyuki Iwata; Yoichi Maeda; Jun Matsushima; Oussama Laouamri; Naveen Khanna; Jeff Mayer; Nilanjan Mukherjee (ITC, 2023)

Test Point Insertion for Multi-Cycle Power-On Self-Test. - Senling Wang; Xihong Zhou; Yoshinobu Higami; Hiroshi Takahashi; Hiroyuki Iwata; Yoichi Maeda; Jun Matsushima (ACM Trans. Design Autom. Electr. Syst., 2023)

Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs. - Hiroyuki Iwata; Mahmoud AbdAlwahab; Ron Press; Ohki Sugiura (ITC, 2024)