Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit. - Koichi Takeda 001; Hidetoshi Ikeda; Yasuhiko Hagihara; Masahiro Nomura; Hiroyuki Kobatake (ISSCC, 2006)

A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. - Koichi Takeda 001; Yasuhiko Hagihara; Yoshiharu Aimoto; Masahiro Nomura; Yoetsu Nakazawa; Toshio Ishii; Hiroyuki Kobatake (IEEE J. Solid State Circuits, 2006)

Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs. - Koichi Takeda 001; Toshio Saito; Shinobu Asayama; Yoshiharu Aimoto; Hiroyuki Kobatake; Shinya Ito; Toshifumi Takahashi; Masahiro Nomura; Kiyoshi Takeuchi; Yoshihiro Hayashi (IEEE J. Solid State Circuits, 2011)