A New Multiport Memory for High Performance Parallel Processor System with Shared Memory. - Keiichi Hirano; Taizou Ono; Hiroyuki Kurino; Mitsumasa Koyanagi (ASP-DAC, 1998)

Future system-on-silicon LSI chips. - Mitsumasa Koyanagi; Hiroyuki Kurino; Kang Wook Lee 002; Katsuyuki Sakuma; Nobuaki Miyakawa; Hikotaro Itani (IEEE Micro, 1998)

Smart Vision Chip Fabricated Using Three Dimensional Integration Technology. - Hiroyuki Kurino; Masaki Nakagawa; Kang Wook Lee 002; Tomonori Nakamura; Yuusuke Yamada; Ki Tae Park; Mitsumasa Koyanagi (NIPS, 2000)

Parallel image processing field programmable gate array for real time image processing system. - Takeaki Sugimura; JeoungChill Shim; Hiroyuki Kurino; Mitsumasa Koyanagi (FPT, 2003)

Design of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory. - Zhe Liu 005; JeoungChill Shim; Hiroyuki Kurino; Mitsumasa Koyanagi (AINA (2), 2004)

Design and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip. - Zhe Liu 005; JeoungChill Shim; Hiroyuki Kurino; Mitsumasa Koyanagi (PDCAT, 2004)

Dynamic Multi-Context Reconfiguration Scheme for Reconfigurable Parallel Image Processing System with Three Dimensional Structure. - Takeaki Sugimura; Yuta Konishi; Yoshihiro Nakatani; Takafumi Fukushima; Hiroyuki Kurino; Mitsumasa Koyanagi (ARCS Workshops, 2005)