A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. - Hiroyuki Mizuno; Nozomu Matsuzaki; Kenichi Osada; Toshinobu Shinbo; Nagatoshi Ohki; Hiroshi Ishida; Koichiro Ishibashi; Tokuo Kure (IEEE J. Solid State Circuits, 1996)

Driving source-line cell architecture for sub-1-V high-speed low-power applications. - Hiroyuki Mizuno; Takahiro Nagano (IEEE J. Solid State Circuits, 1996)

A 1-V programmable DSP for wireless communications [CMOS]. - Wai Lee; Paul E. Landman; Brock Barton; Shigeshi Abiko; Hiroshi Takahashi; Hiroyuki Mizuno; Shigetoshi Muramatsu; Kenichi Tashiro; Masahiro Fusumada; Luat Pham; Frederic Boutaud; Emmanuel Ego; et al. (IEEE J. Solid State Circuits, 1997)

A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. - Masayuki Miyazaki; Hiroyuki Mizuno; Koichiro Ishibashi (ISLPED, 1998)

On the Use of Density Distribution of Keywords for Automated Generation of Hypertext Links from Arbitrary Parts of Documents. - Koichi Kise; Hiroyuki Mizuno; Masashi Yamaguchi; Keinosuke Matsumoto (ICDAR, 1999)

An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode. - Hiroyuki Mizuno; Koichiro Ishibashi; Takanori Shimura; Toshihiro Hattori; Susumu Narita; Kenji Shiozawa; Shuji Ikeda; Kunio Uchiyama (IEEE J. Solid State Circuits, 1999)

A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio. - Hiroyuki Mizuno; Koichiro Ishibashi (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Low-Voltage Embedded-RAM Technology: Present and Future. - Kiyoo Itoh 001; Hiroyuki Mizuno (VLSI-SOC, 2001)

Hierarchical power distribution and power management scheme for a single chip mobile processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (DAC, 2006)

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (ISSCC, 2006)

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution. - Yusuke Kanno; Yuki Kondoh; Takahiro Irita; Kenji Hirose; Ryo Mori; Yoshihiko Yasu; Shigenobu Komatsu; Hiroyuki Mizuno (IEEE J. Solid State Circuits, 2007)

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (IEEE J. Solid State Circuits, 2007)

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. - Masayuki Ito; Toshihiro Hattori; Yutaka Yoshida; Kiyoshi Hayase; Tomoichi Hayashi; Osamu Nishii; Yoshihiko Yasu; Atsushi Hasegawa; Masashi Takada; Hiroyuki Mizuno; Kunio Uchiyama; Toshihiko Odaka; et al. (ISSCC, 2008)

Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. - Masafumi Onouchi; Keisuke Toyama 003; Tohru Nojiri; Makoto Sato; Masayoshi Mase; Jun Shirako; Mikiko Sato; Masashi Takada; Masayuki Ito; Hiroyuki Mizuno; Mitaro Namiki; Keiji Kimura; et al. (ICPP, 2009)

Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. - Kiyoto Ito; Makoto Saen; Kenichi Osada; Tomoyuki Kodama; Hiroyuki Mizuno (3DIC, 2010)

A 45nm 37.3GOPS/W heterogeneous multi-core SoC. - Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Shigezumi Matsui; Osamu Nishii; Atsushi Hasegawa; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Koichi Terada; Tohru Nojiri; et al. (ISSCC, 2010)

Spatial computing architecture using randomness of memory cell stability under voltage control. - Chihiro Yoshimura; Masanao Yamaoka; Hidetaka Aoki; Hiroyuki Mizuno (ECCTD, 2013)

Nonlinear reduced order modeling of plasticization cylinders. - Tomonori Sadamoto; Kenji Kashima; Hiroshi Morita; Hiroyuki Mizuno (ACC, 2014)

An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution. - Masato Hayashi; Masanao Yamaoka; Chihiro Yoshimura; Takuya Okuyama; Hidetaka Aoki; Hiroyuki Mizuno (CANDAR, 2015)

24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing. - Masanao Yamaoka; Chihiro Yoshimura; Masato Hayashi; Takuya Okuyama; Hidetaka Aoki; Hiroyuki Mizuno (ISSCC, 2015)

Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution. - Masato Hayashi; Masanao Yamaoka; Chihiro Yoshimura; Takuya Okuyama; Hidetaka Aoki; Hiroyuki Mizuno (Int. J. Netw. Comput., 2016)

A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing. - Masanao Yamaoka; Chihiro Yoshimura; Masato Hayashi; Takuya Okuyama; Hidetaka Aoki; Hiroyuki Mizuno (IEEE J. Solid State Circuits, 2016)

Sensorimotor Visual Perception on Embodied System Using Free Energy Principle. - Kanako Esaki; Tadayuki Matsumura; Kiyoto Ito; Hiroyuki Mizuno (PKDD/ECML Workshops (1), 2021)

Extended-Self Recognition for Autonomous Agent Based on Controllability and Predictability. - Kanako Esaki; Tadayuki Matsumura; Chihiro Yoshimura; Hiroyuki Mizuno (SSCI, 2022)

Mask Atari for Deep Reinforcement Learning as POMDP Benchmarks. - Yang Shao; Quan Kong; Tadayuki Matsumura; Taiki Fuji; Kiyoto Ito; Hiroyuki Mizuno (CoRR, 2022)

Dynamical Perception-Action Loop Formation with Developmental Embodiment for Hierarchical Active Inference. - Kanako Esaki; Tadayuki Matsumura; Shunsuke Minusa; Yang Shao; Chihiro Yoshimura; Hiroyuki Mizuno (IWAI, 2023)

Quantum Computing from Hype to Game Changer. - Hiroyuki Mizuno (VLSI Technology and Circuits, 2023)

The impact of individual information exchange strategies on the distribution of social wealth. - Yang Shao; Hirokazu Atsumori; Tadayuki Matsumura; Kanako Esaki; Shunsuke Minusa; Hiroyuki Mizuno (CoRR, 2023)

Mixbiotic society measures: Assessment of community well-going as living system. - Takeshi Kato; Junichi Miyakoshi; Tadayuki Matsumura; Ryuji Mine; Hiroyuki Mizuno; Yasuo Deguchi (CoRR, 2023)

Mixbiotic society measures: Comparison of organizational structures based on communication simulation. - Takeshi Kato; Junichi Miyakoshi; Tadayuki Matsumura; Yasuyuki Kudo; Ryuji Mine; Hiroyuki Mizuno; Yasuo Deguchi (CoRR, 2023)

Social Co-OS: Cyber-human social Co-operating system. - Takeshi Kato; Yasuyuki Kudo; Junichi Miyakoshi; Misa Owa; Yasuhiro Asa; Takashi Numata; Ryuji Mine; Hiroyuki Mizuno (IET Cyper-Phys. Syst.: Theory & Appl., 2023)

A cryogenic pulse shaper for spin qubit control utilizing 1ns-time-resolution ADCs on an active silicon interposer operating at sub-100 mK temperatures. - Ryozo Takahashi; Yusuke Kanno; Takuji Miki; Nobuhiro Kusuno; Hiroyuki Mizuno; Makoto Nagata (A-SSCC, 2024)

AI-Facilitation for Consensus-Building by Virtual Discussion Using Large Language Models. - Tadayuki Matsumura; Takeshi Kato; Yasuhiro Asa; Kanako Esaki; Ryuji Mine; Hiroyuki Mizuno (PRICAI (2), 2024)

Response Style Characterization for Repeated Measures Using the Visual Analogue Scale. - Shunsuke Minusa; Tadayuki Matsumura; Kanako Esaki; Yang Shao; Chihiro Yoshimura; Hiroyuki Mizuno (IEEE Access, 2024)

Active Inference With Empathy Mechanism for Socially Behaved Artificial Agents in Diverse Situations. - Tadayuki Matsumura; Kanako Esaki; Shao Yang; Chihiro Yoshimura; Hiroyuki Mizuno (Artif. Life, 2024)

Generating Shuttling Procedures for Constrained Silicon Quantum Dot Array. - Naoto Sato; Tomonori Sekiguchi; Takeru Utsugi; Hiroyuki Mizuno (CoRR, 2024)

Environment-Centric Active Inference. - Kanako Esaki; Tadayuki Matsumura; Takeshi Kato; Shunsuke Minusa; Yang Shao; Hiroyuki Mizuno (CoRR, 2024)

e-person Architecture and Framework for Human-AI Co-adventure Relationship. - Kanako Esaki; Tadayuki Matsumura; Yang Shao; Hiroyuki Mizuno (CoRR, 2025)

Quantum Computer Architecture for Quantum Error Correction With Distributing Process to Multiple Temperature Layers. - Ryuji Ukai; Chihiro Yoshimura; Hiroyuki Mizuno (Concurr. Comput. Pract. Exp., 2025)