Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification. - Hiromi Hiraishi; Kiyoharu Hamaguchi; Hiroyuki Ochi; Shuzo Yajima (CAV, 1991)

Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing. - Hiroyuki Ochi; Nagisa Ishiura; Shuzo Yajima (DAC, 1991)

Breadth-first manipulation of very large binary-decision diagrams. - Hiroyuki Ochi; Koichi Yasuoka; Shuzo Yajima (ICCAD, 1993)

A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. - Hirofumi Sakamoto; Ken'ichiro Uda; Bu-Yeol Lee; Hiroyuki Ochi; Kazuo Taki; Takao Tsuda (ASP-DAC, 2000)

Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation. - Takahiro Kakimoto; Hiroyuki Ochi; Takao Tsuda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers. - Hiroyuki Ochi; Tatsuya Suzuki; Sayaka Matsunaga; Yoichi Kawano; Takao Tsuda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A Localization Scheme for Sensor Networks based onWireless Communication with Anchor Groups. - Hiroyuki Ochi; Shigeaki Tagashira; Satoshi Fujita (ICPADS (1), 2005)

An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD. - Tomonori Izumi; Shin'ichi Kouyama; Hiroyuki Ochi; Yukihiro Nakamura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices. - Kentaro Nakahara; Shin'ichi Kouyama; Tomonori Izumi; Hiroyuki Ochi; Yukihiro Nakamura (FPGA, 2006)

Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells. - Kentaro Nakahara; Shin'ichi Kouyama; Tomonori Izumi; Hiroyuki Ochi; Yukihiro Nakamura (FPL, 2006)

Efficient memory architecture for JPEG2000 entropy codec. - Hiroki Sugano; Hiroshi Tsutsui; Takahiko Masuzaki; Takao Onoye; Hiroyuki Ochi; Yukihiro Nakamura (ISCAS, 2006)

Pedestrian Recognition in Far-Infrared Images by Combining Boosting-Based Detection and Skeleton-Based Stochastic Tracking. - Ryusuke Miyamoto; Hiroki Sugano; Hiroaki Saito; Hiroshi Tsutsui; Hiroyuki Ochi; Ken'ichi Hatanaka; Yukihiro Nakamura (PSIVT, 2006)

Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback. - Kentaro Nakahara; Shin'ichi Kouyama; Tomonori Izumi; Hiroyuki Ochi; Yukihiro Nakamura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A Localization Scheme for Sensor Networks Based on Wireless Communication with Anchor Groups. - Hiroyuki Ochi; Shigeaki Tagashira; Satoshi Fujita (IEICE Trans. Inf. Syst., 2006)

Implementation of AV Streaming System Using Peer-to-Peer Communication. - Norihiro Ishikawa; Hiroshi Tsutsui; Jaehoon Yu; Tomonori Izumi; Hiroyuki Ochi; Yukihiro Nakamura; Takaaki Komura; Yoshitaka Uchida (CCNC, 2007)

Home Appliance Control from Mobile Phones. - Hiromitsu Sumino; Norihiro Ishikawa; Hiroshi Tsutsui; Hiroyuki Ochi; Yukihiro Nakamura; Yoshitaka Uchida (CCNC, 2007)

A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture. - Shin'ichi Kouyama; Tomonori Izumi; Hiroyuki Ochi; Yukihiro Nakamura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Network Processor for High-Speed Network and Quick Programming. - Takahiro Murooka; Akira Nagoya; Toshiaki Miyazaki; Hiroyuki Ochi; Yukihiro Nakamura (J. Circuits Syst. Comput., 2007)

An architecture of photo core transform in HD photo coding system for embedded systems of various bandwidths. - Koichi Hattori; Hiroshi Tsutsui; Hiroyuki Ochi; Yukihiro Nakamura (APCCAS, 2008)

Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device. - Kentaro Nakahara; Shin'ichi Kouyama; Tomonori Izumi; Hiroyuki Ochi; Yukihiro Nakamura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A high-throughput pipelined architecture for JPEG XR encoding. - Koichi Hattori; Hiroshi Tsutsui; Hiroyuki Ochi; Yukihiro Nakamura (ESTIMedia, 2009)

Coarse-grained dynamically reconfigurable architecture with flexible reliability. - Dawood Alnajiar; Younghun Ko; Takashi Imagawa; Hiroaki Konoura; Masayuki Hiromoto; Yukio Mitsuyama; Masanori Hashimoto; Hiroyuki Ochi; Takao Onoye (FPL, 2009)

Hot-Swapping architecture extension for mitigation of permanent functional unit faults. - Zoltan Endre Rakosi; Masayuki Hiromoto; Hiroyuki Ochi; Yukihiro Nakamura (FPL, 2009)

Hardware Architecture for HOG Feature Extraction. - Ryoji Kadota; Hiroki Sugano; Masayuki Hiromoto; Hiroyuki Ochi; Ryusuke Miyamoto; Yukihiro Nakamura (IIH-MSP, 2009)

Dynamic rate control for media streaming in high-speed mobile networks. - Masayuki Hiromoto; Hiroshi Tsutsui; Hiroyuki Ochi; Tomoyuki Osano; Norihiro Ishikawa; Yukihiro Nakamura (WCNC, 2009)

Efficient Memory Organization Framework for JPEG2000 Entropy Codec. - Hiroki Sugano; Takahiko Masuzaki; Hiroshi Tsutsui; Takao Onoye; Hiroyuki Ochi; Yukihiro Nakamura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter. - Hiroki Sugano; Hiroyuki Ochi; Yukihiro Nakamura; Ryusuke Miyamoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA. - Masayuki Hiromoto; Hiroyuki Ochi; Yukihiro Nakamura (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis. - Kentaro Katayama; Shiho Hagiwara; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ICCAD, 2010)

Scan based process parameter estimation through path-delay inequalities. - Takumi Uezono; Tomoyuki Takahashi; Michihiro Shintani; Kazumi Hatayama; Kazuya Masu; Hiroyuki Ochi; Takashi Sato 001 (ISCAS, 2010)

A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. - Takashi Imagawa; Masayuki Hiromoto; Hiroyuki Ochi; Takashi Sato 001 (SoCC, 2010)

Path clustering for adaptive test. - Takumi Uezono; Tomoyuki Takahashi; Michihiro Shintani; Kazumi Hatayama; Kazuya Masu; Hiroyuki Ochi; Takashi Sato 001 (VTS, 2010)

Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. - Takashi Imagawa; Masayuki Hiromoto; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Acceleration of random-walk-based linear circuit analysis using importance sampling. - Tetsuro Miyakawa; Koh Yamanaga; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ACM Great Lakes Symposium on VLSI, 2011)

A fully pipelined implementation of Monte Carlo based SSTA on FPGAs. - Hiroshi Yuasa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ISQED, 2011)

A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization. - Junya Kawashima; Hiroyuki Ochi; Hiroshi Tsutsui; Takashi Sato 001 (SoCC, 2011)

Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices. - Takashi Sato 001; Hiromitsu Awano; Hirofttmi Shimizu; Hiroshi Tsutsui; Hiroyuki Ochi (ISQED, 2012)

Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method. - Hiromitsu Awano; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits. - Junya Kawashima; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A high-throughput pipelined parallel architecture for JPEG XR encoding. - Hiroshi Tsutsui; Koichi Hattori; Hiroyuki Ochi; Yukihiro Nakamura (ACM Trans. Embed. Comput. Syst., 2012)

Realization of frequency-domain circuit analysis through random walk. - Tetsuro Miyakawa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ASP-DAC, 2013)

A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis. - Takashi Imagawa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (DATE, 2013)

Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. - Zoltán Endre Rákossy; Masayuki Hiromoto; Hiroshi Tsutsui; Takashi Sato 001; Yukihiro Nakamura; Hiroyuki Ochi (DATE, 2013)

Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis. - Takumi Morishita; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ACM Great Lakes Symposium on VLSI, 2013)

Multi-trap RTN parameter extraction based on Bayesian inference. - Hiromitsu Awano; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ISQED, 2013)

High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA. - Takashi Imagawa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ISQED, 2013)

Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. - Hiroaki Konoura; Dawood Alnajiar; Yukio Mitsuyama; Hiroyuki Ochi; Takashi Imagawa; Shinichi Noda; Kazutoshi Wakabayashi; Masanori Hashimoto; Takao Onoye (ReConFig, 2013)

Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservation. - Hiroyuki Ochi; Toshihiko Ota; Ataru Yamaoka; Hiromasa Watanabe; Yohei Kondo; Nobuyuki Tokuda; Hiroyuki Taguchi; Taketoshi Matsumoto; Tomoki Akai; Hikaru Kobayashi; Shigeki Imai (SoCC, 2013)

A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis. - Takashi Imagawa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Electron., 2013)

Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element. - Hiroshi Yuasa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Electron., 2013)

Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits. - Takashi Sato 001; Junya Kawashima; Hiroshi Tsutsui; Hiroyuki Ochi (ISQED, 2014)

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. - Hiroaki Konoura; Dawood Alnajiar; Yukio Mitsuyama; Hajime Shimada; Kazutoshi Kobayashi; Hiroyuki Kanbara; Hiroyuki Ochi; Takashi Imagawa; Kazutoshi Wakabayashi; Masanori Hashimoto; Takao Onoye; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. - Masanori Hashimoto; Dawood Alnajiar; Hiroaki Konoura; Yukio Mitsuyama; Hajime Shimada; Kazutoshi Kobayashi; Hiroyuki Kanbara; Hiroyuki Ochi; Takashi Imagawa; Kazutoshi Wakabayashi; Takao Onoye; Hidetoshi Onodera (ASP-DAC, 2015)

Area-efficient LUT-like programmable logic using atom switch and its mapping algorithm. - Toshiki Higashi; Hiroyuki Ochi (ISCIT, 2015)

A -0.5V-input voltage booster circuit for on-chip solar cells in 0.18µm CMOS technology. - Tomoya Kimura; Hiroyuki Ochi (ISCIT, 2015)

An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs. - Takashi Imagawa; Masayuki Hiromoto; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Electron., 2015)

A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. - Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Hiroyuki Ochi; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Kazutoshi Wakabayashi; Hidetoshi Onodera; Yukio Mitsuyama; Masanori Hashimoto (FPL, 2016)

Range Limiter Using Connection Bounding Box for SA-Based Placement of Mixed-Grained Reconfigurable Architecture. - Takashi Kishimoto; Wataru Takahashi 002; Kazutoshi Wakabayashi; Hiroyuki Ochi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain. - Takashi Imagawa; Koki Honda; Hiroyuki Ochi (SoCC, 2017)

Selectable grained reconfigurable architecture (SGRA) and its design automation. - Ryosuke Koike; Takashi Imagawa; Roberto Yusi Omaki; Hiroyuki Ochi (SoCC, 2017)

Area-Efficient LUT-Like Programmable Logic Using Atom Switch and Its Delay-Optimal Mapping Algorithm. - Toshiki Higashi; Hiroyuki Ochi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. - Hiroki Hihara; Akira Iwasaki; Masanori Hashimoto; Hiroyuki Ochi; Yukio Mitsuyama; Hidetoshi Onodera; Hiroyuki Kanbara; Kazutoshi Wakabayashi; Tadahiko Sugibayashi; Takashi Takenaka; Hiromitsu Hada; Munehiro Tada; et al. (IEEE Embed. Syst. Lett., 2018)

Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. - Hiroyuki Ochi; Kosei Yamaguchi; Tetsuaki Fujimoto; Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Takashi Imagawa; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Wataru Takahashi 002; Kazutoshi Wakabayashi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2018)

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. - Masanori Hashimoto; Xu Bai; Naoki Banno; Munehiro Tada; Toshitsugu Sakamoto; Jaehoon Yu; Ryutaro Doi; Yusuke Araki; Hidetoshi Onodera; Takashi Imagawa; Hiroyuki Ochi; Kazutoshi Wakabayashi; et al. (ISSCC, 2020)

Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT. - Takaki Urabe; Hiroyuki Ochi; Kazutoshi Kobayashi (COOL CHIPS, 2021)

MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. - Takashi Imagawa; Jaehoon Yu; Masanori Hashimoto; Hiroyuki Ochi (DATE, 2021)

Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations. - Yuki Abe; Kazutoshi Kobayashi; Jun Shiomi; Hiroyuki Ochi (COOL CHIPS, 2022)

Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations. - Yuki Abe; Kazutoshi Kobayashi; Hiroyuki Ochi (MWSCAS, 2022)

Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction. - Xuanqi Li; Takashi Imagawa; Hiroyuki Ochi (ASICON, 2023)

Approximate Logarithmic Multipliers Using Half Compensation with Two Line Segments. - Renya Makimoto; Takashi Imagawa; Hiroyuki Ochi (SOCC, 2023)

A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor. - Ippei Tanaka; Naoyuki Miyagawa; Tomoya Kimura; Takashi Imagawa; Hiroyuki Ochi (IPSJ Trans. Syst. LSI Des. Methodol., 2023)

Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations. - Yuki Abe; Kazutoshi Kobayashi; Jun Shiomi; Hiroyuki Ochi (IEICE Trans. Electron., 2023)

Foreword. - Hiroyuki Ochi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)