A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive. - Daisaburo Takashima; Susumu Shuto; Iwao Kunishima; Hiroyuki Takenaka; Yukihito Oowaki; Shin'ichi Tanaka (IEEE J. Solid State Circuits, 1999)

A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. - Ryu Ogiwara; Sumio Tanaka; Yasuo Itoh; Tadashi Miyakawa; Yoshiaki Takeuchi; Sumiko Mano Doumae; Hiroyuki Takenaka; Iwao Kunishima; Susumu Shuto; Osamu Hidaka; Sumito Ohtsuki; Shin'ichi Tanaka (IEEE J. Solid State Circuits, 2000)

Interface socket design methodology to generate embedded DRAM macros. - Ryo Haga; Tetsuya Kaneko; Atsushi Nakayama; Shinji Miyano; Hiroyuki Takenaka; Kenji Numata; Hiroyuki Koinuma; Takehiko Hojo; Akikuni Sato; Toshiyuki Kouchi; Kenichiro Mimoto; Masaaki Tazawa; et al. (CICC, 2001)

A 65nm low-power embedded DRAM with extended data-retention sleep mode. - Takeshi Nagai; Masaharu Wada; Hitoshi Iwai; Mariko Kaku; Atsushi Suzuki; Tomohisa Takai; Naoko Itoga; Takayuki Miyazaki; Hiroyuki Takenaka; Takehiko Hojo; Shinji Miyano (ISSCC, 2006)

An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications. - Mariko Kaku; Hitoshi Iwai; Takeshi Nagai; Masaharu Wada; Atsushi Suzuki; Tomohisa Takai; Naoko Itoga; Takayuki Miyazaki; Takayuki Iwai; Hiroyuki Takenaka; Takehiko Hojo; Shinji Miyano; et al. (ISSCC, 2008)