Optimal Code Placement of Embedded Software for Instruction Caches. - Hiroyuki Tomiyama; Hiroto Yasuura (ED&TC, 1996)

Size-Constrained Code Placement for Cache Miss Rate Reduction. - Hiroyuki Tomiyama; Hiroto Yasuura (ISSS, 1996)

Memory-CPU Size Optimization for Embedded System Designs. - Barry Shackleford; Mitsuhiro Yasuda; Etsuko Okushi; Hisao Koizumi; Hiroyuki Tomiyama; Hiroto Yasuura (DAC, 1997)

Code placement techniques for cache miss rate reduction. - Hiroyuki Tomiyama; Hiroto Yasuura (ACM Trans. Design Autom. Electr. Syst., 1997)

Module Selection Using Manufacturing Information. - Hiroyuki Tomiyama; Hiroto Yasuura (ASP-DAC, 1998)

Instruction Scheduling for Power Reduction in Processor-Based System Design. - Hiroyuki Tomiyama; Tohru Ishihara; Akihiko Inoue; Hiroto Yasuura (DATE, 1998)

Instruction Encoding Techniques for Area Minimization of Instruction ROM. - Takanori Okuma; Hiroyuki Tomiyama; Akihiko Inoue; Eko Fajar; Hiroto Yasuura (ISSS, 1998)

Statistical Performance-Driven Module Binding in High-Level Synthesis. - Hiroyuki Tomiyama; Akihiko Inoue; Hiroto Yasuura (ISSS, 1998)

Embedded System Design Using Soft-Core Processor and Valen-C. - Hiroto Yasuura; Hiroyuki Tomiyama; Akihiko Inoue; Eko Fajar (J. Inf. Sci. Eng., 1998)

Program path analysis to bound cache-related preemption delay in preemptive real-time systems. - Hiroyuki Tomiyama; Nikil D. Dutt (CODES, 2000)

Verification of in-order execution in pipelined processors. - Hiroyuki Tomiyama; Taisei Yoshino; Nikil D. Dutt (HLDVT, 2000)

New directions in compiler technology for embedded systems (embedded tutorial). - Nikil D. Dutt; Alexandru Nicolau; Hiroyuki Tomiyama; Ashok Halambi (ASP-DAC, 2001)

Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique. - Anupam Datta; Sidharth Choudhury; Anupam Basu; Hiroyuki Tomiyama; Nikil D. Dutt (VLSI Design, 2001)

Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. - Prabhat Mishra 001; Nikil D. Dutt; Alexandru Nicolau; Hiroyuki Tomiyama (DATE, 2002)

Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. - Hiroto Yasuura; Hiroyuki Tomiyama; Takanori Okuma; Yun Cao (ISSS, 2002)

Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. - Prabhat Mishra 001; Hiroyuki Tomiyama; Ashok Halambi; Peter Grun; Nikil D. Dutt; Alexandru Nicolau (ASP-DAC/VLSI Design, 2002)

Data Organization Exploration for Low-Energy Address Buses. - Hiroyuki Tomiyama; Hiroaki Takada; Nikil D. Dutt (ESTIMedia, 2003)

Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications. - Prabhat Mishra 001; Nikil D. Dutt; Hiroyuki Tomiyama (Des. Autom. Embed. Syst., 2003)

RTOS-centric hardware/software cosimulator for embedded system design. - Shinya Honda; Takayuki Wakabayashi; Hiroyuki Tomiyama; Hiroaki Takada (CODES+ISSS, 2004)

ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts. - Hiroyuki Tomiyama; Nikil D. Dutt (IEICE Trans. Inf. Syst., 2004)

A GA-based scheduling method for FlexRay systems. - Shan Ding; Naohiko Murakami; Hiroyuki Tomiyama; Hiroaki Takada (EMSOFT, 2005)

Cosimulation of ITRON-based embedded software with SystemC. - Shin-ichiro Chikada; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (HLDVT, 2005)

An Efficient Search Algorithm of Worst-Case Cache Flush Timings. - Hiroshi Miyamoto; Shinichi Iiyama; Hiroyuki Tomiyama; Hiroaki Takada; Hiroshi Nakashima (RTCSA, 2005)

An RTOS-Based Design and Validation Methodology for Embedded Systems. - Hiroyuki Tomiyama; Shin-ichiro Chikada; Shinya Honda; Hiroaki Takada (IEICE Trans. Inf. Syst., 2005)

NEXCESS: Nagoya university extension courses for embedded software specialists. - Masaki Yamamoto 004; Hiroyuki Tomiyama; Hiroaki Takada; Kiyoshi Agusa; Kenji Mase; Nobuo Kawaguchi; Shinya Honda; Nobuyuki Kaneko (SIGBED Rev., 2005)

Function Call Optimization in Behavioral Synthesis. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (DSD, 2006)

RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip. - Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (ASP-DAC, 2007)

A Software Framework for Energy and Performance Tradeoff in Fixed-Priority Hard Real-Time Embedded Systems. - Gang Zeng; Hiroyuki Tomiyama; Hiroaki Takada (EUC, 2007)

Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada; Katsuya Ishii (ACM Great Lakes Symposium on VLSI, 2007)

A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems. - Takashi Furukawa; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (ICESS, 2007)

Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada; Katsuya Ishii (ICESS, 2007)

Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services. - Gang Zeng; Hiroyuki Tomiyama; Hiroaki Takada (IESS, 2007)

Scheduling Algorithms for I/O Blockings with a Multi-frame Task Model. - Shan Ding; Hiroyuki Tomiyama; Hiroaki Takada (RTCSA, 2007)

Function Call Optimization for Efficient Behavioral Synthesis. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada; Katsuya Ishii (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Practice and analysis of an extension course for training trainers of embedded software. - Masaki Yamamoto 004; Shinya Honda; Hiroaki Takada; Kiyoshi Agusa; Hiroyuki Tomiyama; Kenji Mase; Nobuo Kawaguchi; Nobuyuki Kaneko (SIGBED Rev., 2007)

Improved Policies for Drowsy Caches in Embedded Processors. - Junpei Zushi; Gang Zeng; Hiroyuki Tomiyama; Hiroaki Takada; Koji Inoue (DELTA, 2008)

A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems. - Gang Zeng; Hiroyuki Tomiyama; Hiroaki Takada; Tohru Ishihara (EUC (1), 2008)

Energy Efficiency of Scratch-Pad Memory at 65 nm and Below: An Empirical Study. - Hideki Takase; Hiroyuki Tomiyama; Gang Zeng; Hiroaki Takada (ICESS, 2008)

CHStone: A benchmark program suite for practical C-based high-level synthesis. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada; Katsuya Ishii (ISCAS, 2008)

Energy efficiency of scratch-pad memory in deep submicron domains: an empirical study. - Hideki Takase; Hiroyuki Tomiyama; Gang Zeng; Hiroaki Takada (IEICE Electron. Express, 2008)

An Effective GA-Based Scheduling Algorithm for FlexRay Systems. - Shan Ding; Hiroyuki Tomiyama; Hiroaki Takada (IEICE Trans. Inf. Syst., 2008)

High-Level Synthesis of Software Function Calls. - Masanari Nishimura; Nagisa Ishiura; Yoshiyuki Ishimori; Hiroyuki Kanbara; Hiroyuki Tomiyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Embedded System Covalidation with RTOS Model and FPGA. - Seiya Shibata; Shinya Honda; Yuko Hara; Hiroyuki Tomiyama; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Dynamic Power Management for Embedded System Idle State in the Presence of Periodic Interrupt Services. - Gang Zeng; Hiroyuki Tomiyama; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Analyzing and optimizing energy efficiency of algorithms on DVS systems a first step towards algorithmic energy minimization. - Tetsuo Yokoyama; Gang Zeng; Hiroyuki Tomiyama; Hiroaki Takada (ASP-DAC, 2009)

Heuristics for Static Voltage Scheduling Algorithms on Battery-Powered DVS Systems. - Tetsuo Yokoyama; Gang Zeng; Hiroyuki Tomiyama; Hiroaki Takada (ICESS, 2009)

Practical Energy-Aware Scheduling for Real-Time Multiprocessor Systems. - Gang Zeng; Tetsuo Yokoyama; Hiroyuki Tomiyama; Hiroaki Takada (RTCSA, 2009)

Effective Scheduling Algorithms for I/O Blocking with a Multi-Frame Task Model. - Shan Ding; Hiroyuki Tomiyama; Hiroaki Takada (IEICE Trans. Inf. Syst., 2009)

Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems. - Hideki Takase; Hiroyuki Tomiyama; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

A Generalized Framework for Energy Savings in Hard Real-Time Embedded Systems. - Gang Zeng; Hiroyuki Tomiyama; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (J. Inf. Process., 2009)

Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems. - Lovic Gauthier; Tohru Ishihara; Hideki Takase; Hiroyuki Tomiyama; Hiroaki Takada (CASES, 2010)

Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems. - Hideki Takase; Hiroyuki Tomiyama; Hiroaki Takada (DATE, 2010)

Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis. - Toshinobu Matsuba; Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (DELTA, 2010)

A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems. - Krzysztof Jozwik; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (FPL, 2010)

Automatic communication synthesis with hardware sharing for design space exploration. - Yuki Ando; Seiya Shibata; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (ISCAS, 2010)

Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design. - Yuki Ando; Seiya Shibata; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems. - Tetsuo Yokoyama; Gang Zeng; Hiroyuki Tomiyama; Hiroaki Takada (IEICE Trans. Inf. Syst., 2010)

Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation. - Seiya Shibata; Yuki Ando; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Checkpoint Extraction Using Execution Traces for Intra-task DVFS in Embedded Systems. - Tomohiro Tatematsu; Hideki Takase; Gang Zeng; Hiroyuki Tomiyama; Hiroaki Takada (DELTA, 2011)

An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating. - Ittetsu Taniguchi; Mitsuya Uchida; Hiroyuki Tomiyama; Masahiro Fukui; Praveen Raghavan; Francky Catthoor (DSD, 2011)

An integrated optimization framework for reducing the energy consumption of embedded real-time applications. - Hideki Takase; Gang Zeng; Lovic Gauthier; Hirotaka Kawashima; Noritoshi Atsumi; Tomohiro Tatematsu; Yoshitake Kobayashi; Shunitsu Kohara; Takenori Koshiro; Tohru Ishihara; Hiroyuki Tomiyama; Hiroaki Takada (ISLPED, 2011)

Fast design space exploration for mixed hardware-software embedded systems. - Yuki Ando; Seiya Shibata; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (ISOCC, 2011)

Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems. - Krzysztof Jozwik; Hiroyuki Tomiyama; Masato Edahiro; Shinya Honda; Hiroaki Takada (ISOCC, 2011)

Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs. - Krzysztof Jozwik; Hiroyuki Tomiyama; Masato Edahiro; Shinya Honda; Hiroaki Takada (ReConFig, 2011)

Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems. - Hideki Takase; Hiroyuki Tomiyama; Hiroaki Takada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Clock-constrained simultaneous allocation and binding for multiplexer optimization in high-level synthesis. - Yuko Hara; Hiroyuki Tomiyama (ASP-DAC, 2012)

Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis. - Yuko Hara-Azumi; Toshinobu Matsuba; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (HPCC-ICESS, 2012)

A Fast Network-on-Chip Simulator with QEMU and SystemC. - Keita Nakajima; Takuji Hieda; Ittetsu Taniguchi; Hiroyuki Tomiyama; Hiroaki Takada (ICNC, 2012)

Task mapping techniques for embedded many-core SoCs. - Junya Kaida; Takuji Hieda; Ittetsu Taniguchi; Hiroyuki Tomiyama; Yuko Hara-Azumi; Koji Inoue (ISOCC, 2012)

Energy-aware SA-based instruction scheduling for fine-grained power-gated VLIW processors. - Mitsuya Uchida; Ittetsu Taniguchi; Hiroyuki Tomiyama; Masahiro Fukui (ISOCC, 2012)

Comparison of Preemption Schemes for Partially Reconfigurable FPGAs. - Krzysztof Jozwik; Hiroyuki Tomiyama; Masato Edahiro; Shinya Honda; Hiroaki Takada (IEEE Embed. Syst. Lett., 2012)

A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs. - Krzysztof Jozwik; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (IEICE Trans. Inf. Syst., 2012)

A Fast Performance Estimation Framework for System-Level Design Space Exploration. - Seiya Shibata; Yuki Ando; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

SMYLE OpenCL: A programming framework for embedded many-core SoCs. - Hiroyuki Tomiyama; Takuji Hieda; Naoki Nishiyama; Noriko Etani; Ittetsu Taniguchi (ASP-DAC, 2013)

List Scheduling Strategies for Task Graphs with Data Parallelism. - Yang Liu 001; Ittetsu Taniguchi; Hiroyuki Tomiyama; Lin Meng (CANDAR, 2013)

Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration. - Yuki Ando; Seiya Shibata; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (IESS, 2013)

Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation. - Yuko Hara-Azumi; Hiroyuki Tomiyama (ISQED, 2013)

Function profiling for embedded software by utilizing QEMU and analyzer tool. - Tran Van Dung; Ittetsu Taniguchi; Takuji Hieda; Hiroyuki Tomiyama (MWSCAS, 2013)

Static Mapping of Multiple Data-Parallel Applications on Embedded Many-Core SoCs. - Junya Kaida; Yuko Hara-Azumi; Takuji Hieda; Ittetsu Taniguchi; Hiroyuki Tomiyama; Koji Inoue (IEICE Trans. Inf. Syst., 2013)

Naxim: A Fast and Retargetable Network-on-Chip Simulator with QEMU and SystemC. - Keita Nakajima; Shuto Kurebayashi; Yusuke Fukutsuka; Takuji Hieda; Ittetsu Taniguchi; Hiroyuki Tomiyama; Hiroaki Takada (Int. J. Netw. Comput., 2013)

Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs. - Krzysztof Jozwik; Shinya Honda; Masato Edahiro; Hiroyuki Tomiyama; Hiroaki Takada (Int. J. Reconfigurable Comput., 2013)

Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks. - Yuko Hara-Azumi; Toshinobu Matsuba; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

A dual-mode scheduling algorithm for task graphs with data parallelism. - Yang Liu 001; Lin Meng; Ittetsu Taniguchi; Hiroyuki Tomiyama (APCCAS, 2014)

Cache Simulation for Instruction Set Simulator QEMU. - Tran Van Dung; Ittetsu Taniguchi; Hiroyuki Tomiyama (DASC, 2014)

Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs. - Yuki Ando; Seiya Shibata; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (FCCM, 2014)

Task Migration for Energy Saving in Real-Time Multiprocessor Systems. - Gang Zeng; Yutaka Matsubara; Hiroyuki Tomiyama; Hiroaki Takada (HPCC/CSS/ICESS, 2014)

An Integrated Framework for Energy Optimization of Embedded Real-Time Applications. - Hideki Takase; Gang Zeng; Lovic Gauthier; Hirotaka Kawashima; Noritoshi Atsumi; Tomohiro Tatematsu; Yoshitake Kobayashi; Takenori Koshiro; Tohru Ishihara; Hiroyuki Tomiyama; Hiroaki Takada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path. - Ittetsu Taniguchi; Kohei Aoki; Hiroyuki Tomiyama; Praveen Raghavan; Francky Catthoor; Masahiro Fukui (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-Core SoCs. - Ittetsu Taniguchi; Junya Kaida; Takuji Hieda; Yuko Hara-Azumi; Hiroyuki Tomiyama (IEICE Trans. Inf. Syst., 2014)

Novel List Scheduling Strategies for Data Parallelism Task Graphs. - Yang Liu 001; Lin Meng; Ittetsu Taniguchi; Hiroyuki Tomiyama (Int. J. Netw. Comput., 2014)

Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs. - Yuko Hara-Azumi; Toshinobu Matsuba; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

Message from the Editor-in-Chief. - Hiroyuki Tomiyama (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

Profiling-driven multi-cycling in FPGA high-level synthesis. - Stefan Hadjis; Andrew Canis; Ryoya Sobue; Yuko Hara-Azumi; Hiroyuki Tomiyama; Jason Helge Anderson (DATE, 2015)

Comparison of Thread Execution Methods for GPU-oriented OpenCL Programs on Multicore Processors. - Naohisa Hojo; Ittetsu Taniguchi; Hiroyuki Tomiyama (EWiLi, 2015)

Function-level profiling for embedded software with QEMU. - Tran Van Dung; Ittetsu Taniguchi; Takuji Hieda; Hiroyuki Tomiyama (Int. J. Embed. Syst., 2015)

A systematic methodology for design and analysis of approximate array multipliers. - Takahiro Yamamoto; Ittetsu Taniguchi; Hiroyuki Tomiyama; Shigeru Yamashita; Yuko Hara-Azumi (APCCAS, 2016)

Energy-aware task migration for multiprocessor real-time systems. - Gang Zeng; Yutaka Matsubara; Hiroyuki Tomiyama; Hiroaki Takada (Future Gener. Comput. Syst., 2016)

Static Mapping of Multiple Parallel Applications on Non-Hierarchical Manycore Embedded Systems. - Yining Xu; Yang Liu 001; Junya Kaida; Ittetsu Taniguchi; Hiroyuki Tomiyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Power Measurement and Modeling of Quadcopters on Horizontal Flight. - Kotaro Maekawa; Shunsuke Negoro; Ittetsu Taniguchi; Hiroyuki Tomiyama (CANDAR, 2017)

Binary synthesis implementing external interrupt handler as independent module. - Naoya Ito; Yuuki Oosako; Nagisa Ishiura; Hiroyuki Kanbara; Hiroyuki Tomiyama (RSP, 2017)

ILP-Based Scheduling for Parallelizable Tasks. - Kana Shimada; Shogo Kitano; Ittetsu Taniguchi; Hiroyuki Tomiyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Static Mapping of Parallelizable Tasks under Deadline Constraints. - Yining Xu; Ittetsu Taniguchi; Hiroyuki Tomiyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers. - Takahiro Yamamoto; Ittetsu Taniguchi; Hiroyuki Tomiyama; Shigeru Yamashita; Yuko Hara-Azumi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A dual-mode scheduling approach for task graphs with data parallelism. - Yang Liu 001; Lin Meng; Ittetsu Taniguchi; Hiroyuki Tomiyama (Int. J. Embed. Syst., 2017)

Communication-aware scheduling of data-parallel tasks: work-in-progress. - Kana Shimada; Ittetsu Taniguchi; Hiroyuki Tomiyama (CASES, 2018)

Revisiting Thread Execution Methods for GPU-Oriented OpenCL Programs on Multicore Processors. - Takafumi Miyazaki; Hayato Hidari; Naohisa Hojo; Ittetsu Taniguchi; Hiroyuki Tomiyama (CANDAR Workshops, 2018)

Scheduling of Malleable Fork-Join Tasks with Constraint Programming. - Hiroki Nishikawa; Kana Shimada; Ittetsu Taniguchi; Hiroyuki Tomiyama (CANDAR, 2018)

A Case Study on Memory Architecture Exploration for Manycores on an FPGA. - Seiya Shirakuni; Ittetsu Taniguchi; Hiroyuki Tomiyama (CANDAR Workshops, 2018)

A HOG-SVM Based Fall Detection IoT System for Elderly Persons Using Deep Sensor. - Xiangbo Kong; Zelin Meng; Naoto Nojiri; Yuji Iwahori; Lin Meng; Hiroyuki Tomiyama (IIKI, 2018)

Synthesis of Full Hardware Implementation of RTOS-Based Systems. - Yuuki Oosako; Nagisa Ishiura; Hiroyuki Tomiyama; Hiroyuki Kanbara (RSP, 2018)

Scheduling of Malleable Tasks Based on Constraint Programming. - Hiroki Nishikawa; Kana Shimada; Ittetsu Taniguchi; Hiroyuki Tomiyama (TENCON, 2018)

A Web-Based Routing and Visualization Tool for Drone Delivery. - Takuma Hikida; Yusuke Funabashi; Hiroyuki Tomiyama (CANDAR Workshops, 2019)

Lucas-Kanade Optical Flow Based Camera Motion Estimation Approach. - Zelin Meng; Xiangbo Kong; Lin Meng; Hiroyuki Tomiyama (ISOCC, 2019)

Function-Level Module Sharing in High-Level Synthesis. - Ryohei Nozaki; Hiroki Nishikawa; Ittetsu Taniguchi; Hiroyuki Tomiyama (ISOCC, 2019)

Scheduling of Malleable Tasks with DMA-based Communication. - Kana Shimada; Takuma Hikida; Hiroki Nishikawa; Ittetsu Taniguchi; Hiroyuki Tomiyama (ISOCC, 2019)

Maximum Error-Aware Design of Approximate Array Multipliers. - Kenta Shirane; Takahiro Yamamoto; Ittetsu Taniguchi; Yuko Hara-Azumi; Shigeru Yamashita; Hiroyuki Tomiyama (ISOCC, 2019)

Work-in-Progress: Routing of Delivery Drones with Load-Dependent Flight Speed. - Yusuke Funabashi; Ittetsu Taniguchi; Hiroyuki Tomiyama (RTSS, 2019)

A Constraint Programming Approach to Scheduling of Malleable Tasks. - Hiroki Nishikawa; Kana Shimada; Ittetsu Taniguchi; Hiroyuki Tomiyama (Int. J. Netw. Comput., 2019)

QoE-Constrained Concurrent Request Optimization Through Collaboration of Edge Servers. - Yaqiang Zhang; Lin Meng; Xiao Xue 001; Zhangbing Zhou; Hiroyuki Tomiyama (IEEE Internet Things J., 2019)

A Genetic Algorithm for Scheduling of Data-parallel Tasks on Multicore Architectures. - Yang Liu 001; Lin Meng; Hiroyuki Tomiyama (IPSJ Trans. Syst. LSI Des. Methodol., 2019)

An OpenCL-based Software Framework for a Heterogeneous Multicore Architecture on Zynq-7000 SoC. - Takafumi Miyazaki; Shunsuke Takai; Ittetsu Taniguchi; Hiroyuki Tomiyama (IPSJ Trans. Syst. LSI Des. Methodol., 2019)

Communication-Aware Scheduling of Data-Parallel Tasks on Multicore Architectures. - Kana Shimada; Ittetsu Taniguchi; Hiroyuki Tomiyama (IPSJ Trans. Syst. LSI Des. Methodol., 2019)

Design and Evaluation of Asymmetric and Symmetric 32-core Architectures on FPGA. - Seiya Shirakuni; Ittetsu Taniguchi; Hiroyuki Tomiyama (IPSJ Trans. Syst. LSI Des. Methodol., 2019)

Three-States-Transition Method for Fall Detection Algorithm Using Depth Image. - Xiangbo Kong; Zelin Meng; Lin Meng; Hiroyuki Tomiyama (J. Robotics Mechatronics, 2019)

Robust Self-Adaptation Fall-Detection System Based on Camera Height. - Xiangbo Kong; Lehan Chen; Zhichen Wang; Yuxi Chen; Lin Meng; Hiroyuki Tomiyama (Sensors, 2019)

Energy-aware scheduling of malleable fork-join tasks under a deadline constraint on heterogeneous multicores. - Hiroki Nishikawa; Kana Shimada; Ittetsu Taniguchi; Hiroyuki Tomiyama (SIGBED Rev., 2019)

ILP-based scheduling for malleable fork-join tasks. - Kana Shimada; Ittetsu Taniguchi; Hiroyuki Tomiyama (SIGBED Rev., 2019)

Frame Detection and Text Line Segmentation for Early Japanese Books Understanding. - Bing Lyu; Hiroyuki Tomiyama; Lin Meng (ICPRAM, 2020)

Heuristic Algorithms for Dynamic Scheduling of Moldable Tasks. - Takuma Hikida; Hiroki Nishikawa; Hiroyuki Tomiyama (ISOCC, 2020)

A Quadcopters Flight Simulation Considering the Influence of Wind. - Mayu Ida; Hiroki Nishikawa; Xiangbo Kong; Ittetsu Taniguchi; Hiroyuki Tomiyama (ISOCC, 2020)

A Case Study on Rubbing Character Recognition Based on Deep Learning. - Zelin Meng; Zhiyu Zhang; Lin Meng; Hiroyuki Tomiyama (ISOCC, 2020)

Scheduling of Rigid Tasks on Heterogeneous Multicores. - Takava Watanabe; Hiroki Nishikawa; Hiroyuki Tomiyama (ISOCC, 2020)

An Evaluation of Edge Computing Platform for Reliable Automated Drones. - Jo Yoshimoto; Ittetsu Taniguchi; Hiroyuki Tomiyama; Takao Onoye (ISOCC, 2020)

Scheduling of moldable fork-join tasks with inter- and intra-task communications. - Hiroki Nishikawa; Kana Shimada; Ittetsu Taniguchi; Hiroyuki Tomiyama (SCOPES, 2020)

A branch-and-bound approach to scheduling of data-parallel tasks on multi-core architectures. - Yang Liu 001; Lin Meng; Ittetsu Taniguchi; Hiroyuki Tomiyama (Int. J. Embed. Syst., 2020)

A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones. - Yusuke Funabashi; Atsuya Shibata; Shunsuke Negoro; Ittetsu Taniguchi; Hiroyuki Tomiyama (IPSJ Trans. Syst. LSI Des. Methodol., 2020)

Routing of Delivery Drones Considering Load and Wind Effects. - Satoshi Ito; Keishi Akaiwa; Yusuke Funabashi; Hiroki Nishikawa; Xiangbo Kong; Ittetsu Taniguchi; Hiroyuki Tomiyama (ATAIT, 2021)

Frailty Classification Based on Artificial Intelligence. - Zelin Meng; Lin Meng; Kenshi Saho; Xiangbo Kong; Hiroyuki Tomiyama (ATAIT, 2021)

Pix2Pix-Based Depth Estimation from Monocular Images for Dynamic Path Planning of Multirotor on AirSim. - Tomoyasu Shimada; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ATAIT, 2021)

Minimization of Routing Area in MEDA Biochips. - Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita (BioCAS, 2021)

A Home Security Camera System with Container-based Resource Allocation on Raspberry Pi. - Takuya Egashira; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ICEIC, 2021)

A Comprehensive Analysis of Low-Impact Computations in Deep Learning Workloads. - Hengyi Li; Zhichen Wang; Xuebin Yue; Wenwen Wang 001; Hiroyuki Tomiyama; Lin Meng (ACM Great Lakes Symposium on VLSI, 2021)

Impacts of HLS Optimizations on Side-Channel Leakage for AES Circuits. - Takumi Mizuno; Qidi Zhang; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ISOCC, 2021)

Scheduling with Variable-Cycle Approximate Functional Units in High-Level Synthesis. - Koyu Ohata; Kenta Shirane; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ISOCC, 2021)

Design of a 32-bit Accuracy-Controllable Approximate Multiplier for FPGAs. - Masaki Sano; Kenta Shirane; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Tongxin Yang; Tomoaki Ukezono (ISOCC, 2021)

High-Level Synthesis of Approximate Computing Circuits with Dual Accuracy Modes. - Kenta Shirane; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ISOCC, 2021)

Power Side-Channel Analysis for Different Adders on FPGA. - Yilin Zhao; Qidi Zhang; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ISOCC, 2021)

Energy-aware Routing of Delivery Drones under Windy Conditions. - Satoshi Ito; Hiroki Nishikawa; Xiangbo Kong; Yusuke Funabashi; Atsuya Shibata; Shunsuke Negoro; Ittetsu Taniguchi; Hiroyuki Tomiyama (IPSJ Trans. Syst. LSI Des. Methodol., 2021)

A Case Study on Forehand Footwork Mistake Detection in Table Tennis. - Hiroki Matsumiya; Xiangbo Kong; Ami Tanaka; Hiroki Nishikawa; Hiroyuki Tomiyama (ATAIT, 2022)

Delivery Drone Routing under Load-dependent Flight Speed based on Integer Quadratic Programming. - Mao Nishira; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ATAIT, 2022)

A Heuristic Scheduling Algorithm with Variable-Cycle Approximate Functional Units in High-Level Synthesis. - Koyu Ohata; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ATAIT, 2022)

An Accuracy-Controllable Approximate Adder for FPGAs. - Masaki Sano; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Tongxin Yang; Tomoaki Ukezono; Toshinori Sato (ATAIT, 2022)

Monocular Thermal Camera Depth Estimation with Optical Flow for Autonomous Drones. - Tomoyasu Shimada; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ATAIT, 2022)

Evaluation of Power Analysis Attack Resistance of Masked Adders on FPGA. - Yilin Zhao; Qidi Zhang; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ATAIT, 2022)

An ILP-based Approach to Delivery Drone Routing under Load-dependent Flight Speed. - Mao Nishira; Satoshi Ito; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ICEIC, 2022)

Depth Estimation from Monocular Infrared Images for Autonomous Flight of Drones. - Tomoyasu Shimada; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ICEIC, 2022)

Priority-aware Static Task Mapping for Edge-Cloud Platforms. - Jo Yoshimoto; Ittetsu Taniguchi; Hiroyuki Tomiyama; Takao Onoye (ICEIC, 2022)

Energy Consumption Reduction through Resource Allocation Using Docker. - Eiji Sugahara; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (CANDARW, 2022)

Fusing Infrared and Visible Images for DNN-based Nighttime Human Detection. - Wanyin Shi; Hiroki Matsumiya; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ISOCC, 2022)

Monocular Depth Estimation with Optical Flow Attention for Autonomous Drones. - Tomoyasu Shimhada; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ISOCC, 2022)

A Fair-Policy Dynamic Scheduling Algorithm for Moldable Gang Tasks on Multicores. - Tomoki Shimizu; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (MECO, 2022)

Container-based Throughput Balancing for Multiple Streaming Applications: A Case Study. - Yuho Toku; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (MECO, 2022)

Shape-Dependent Velocity Based Droplet Routing on MEDA Biochips. - Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita; Sudip Roy 001 (IEEE Access, 2022)

ILP-Based and Heuristic Scheduling Techniques for Variable-Cycle Approximate Functional Units in High-Level Synthesis. - Koyu Ohata; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (Comput., 2022)

Simultaneous Scheduling and Core-Type Optimization for Moldable Fork-Join Tasks on Heterogeneous Multicores. - Hiroki Nishikawa; Kana Shimada; Ittetsu Taniguchi; Hiroyuki Tomiyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Mouldable fork-join task scheduling techniques with inter and intra-task communications. - Hiroki Nishikawa; Kana Shimada; Ittetsu Taniguchi; Hiroyuki Tomiyama (Int. J. Embed. Syst., 2022)

Pix2Pix-Based Monocular Depth Estimation for Drones with Optical Flow on AirSim. - Tomoyasu Shimada; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (Sensors, 2022)

In/Out Judgement by Ball Tracking in Table Tennis. - Yuta Fujihara; Xiangbo Kong; Ami Tanaka; Hiroki Nishikawa; Hiroyuki Tomiyama (ATAIT, 2023)

Faster Depth Estimation for Autonomous Flying Drones. - Takuya Kosaka; Xiangbo Kong; Tomoyasu Shimada; Hiroki Nishikawa; Hiroyuki Tomiyama (ATAIT, 2023)

Drone path planning method to reduce energy consumption. - Takuto Maejima; Xiangbo Kong; Tomoyasu Shimada; Hiroki Nishikawa; Hiroyuki Tomiyama (ATAIT, 2023)

Ball Touching Net Detection Using Piezoelectric Element in Table Tennis. - Ruisheng Xu; Ami Tanaka; Xiangbo Kong; Hiroyuki Tomiyama (ATAIT, 2023)

Design and Evaluation of AES Encryption Circuits with Various S-Box Implementation. - Taosong Zhao; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ATAIT, 2023)

Simulation-based Analysis of Power Side-Channel Leakage at Different Sampling Intervals. - Yuto Miura; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (CANDARW, 2023)

Surveillance Routing with a Minimum Number of Drones. - Kaito Mori; Mao Nishira; Hiroki Nishikawa; Hiroyuki Tomiyama (CANDARW, 2023)

Impacts of Clock Constraints on Side-Channel Leakage of HLS-designed AES Circuits. - Yuto Miura; Takumi Mizuno; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ICEIC, 2023)

Empirical Analysis of Side-Channel Attack Resistance of HLS-designed AES Circuits. - Takumi Mizuno; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ICEIC, 2023)

Multi-Droplet Routing based on a Shape-Dependent Velocity Model on MEDA Biochips. - Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita (ICEIC, 2023)

A Deep Reinforcement Learning-based Routing Algorithm for Unknown Erroneous Cells in DMFBs. - Tomohisa Kawakami; Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita (NEWCAS, 2023)

A Fast Approach to Droplet Routing with Shape-Dependent Velocity on MEDA Biochips. - Kaito Mori; Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita (NEWCAS, 2023)

Message from the Chairs: RTCSA 2023. - Hiroshi Yamada; Ting He; Hiroyuki Tomiyama; Nan Guan; Sebastian Steinhorst (RTCSA, 2023)

Transport-Free Placement of Mixers for Realizing Bioprotocol on Programmable Microfluidic Devices. - Masataka Hirai; Debraj Kundu; Shigeru Yamashita; Sudip Roy 001; Hiroyuki Tomiyama (VLSID, 2023)

An architecture-level analysis on deep learning models for low-impact computations. - Hengyi Li; Zhichen Wang; Xuebin Yue; Wenwen Wang 001; Hiroyuki Tomiyama; Lin Meng (Artif. Intell. Rev., 2023)

Rice Yield Prediction in Different Growth Environments Using Unmanned Aerial Vehicle-Based Hyperspectral Imaging. - Junichi Kurihara; Toru Nagata; Hiroyuki Tomiyama (Remote. Sens., 2023)

A Deep Reinforcement Learning Approach to Droplet Routing for Erroneous Digital Microfluidic Biochips. - Tomohisa Kawakami; Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita (Sensors, 2023)

Evaluation of Self-localization Estimation in Indoor Environments Using Cameras for Small Drones. - Genki Higashiuchi; Tomoyasu Shimada; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ATAIT, 2024)

Simultaneous Routing with Washing Droplets in MEDA Biochips. - Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita (ATAIT, 2024)

Spin Estimation for Back Spin Serves in Table Tennis Using Racket Speed and Angle. - Hiroki Matsumiya; Xiangbo Kong; Ami Tanaka; Hiroki Nishikawa; Hiroyuki Tomiyama (ICEIC, 2024)

Impacts of Clock Frequency and Sampling Intervals on Power Side-Channel Leakage of AES Circuits. - Yuto Miura; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ICEIC, 2024)

Multi-Trip Routing of Delivery Drones with Load-Dependent Flight Speed. - Mao Nishira; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ICEIC, 2024)

Fast 32-bit and 48-bit Multipliers for FPGA. - Wakana Ohashi; Aoi Yamaguch; Hiroki Nishikawa; Hiroyuki Tomiyama (ICEIC, 2024)

A Non-Work Conserving Algorithm for Dynamic Scheduling of Moldable Gang Tasks on Multicore Systems. - Tomoki Shimizu; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ICEIC, 2024)

Interval-Aware Scheduling of a Surveillance Drone. - Kaito Mori; Hiroki Nishikawa; Hiroyuki Tomiyama (GCCE, 2024)

An Approximate Multiplier Design Based on Mitchell's Algorithm. - Xiangyu Li; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ISOCC, 2024)

FPGA Design of a Masked AES Circuit with PPRM-based S-Box. - Yuhui Liu; Taosong Zhao; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama (ISOCC, 2024)

YOLO-UTS: Lightweight YOLOv5 for UAV Traffic Monitoring and Surveillance. - Haimin Yan; Juncheng Wang; Xiangbo Kong; Hiroyuki Tomiyama (SMC, 2024)

YOLO-ELD: Efficient and Lightweight Detection for UAV Aerial Imagery. - Haimin Yan; Juncheng Wang; Xiangbo Kong; Hiroyuki Tomiyama (SMC, 2024)

Table Tennis Stroke Classification from Game Videos Using 3D Human Keypoints. - Yuta Fujihara; Xiangbo Kong; Ami Tanaka; Hiroki Nishikawa; Hiroyuki Tomiyama (VCIP, 2024)

Dynamic Point-Pixel Feature Alignment for Multimodal 3-D Object Detection. - Juncheng Wang; Xiangbo Kong; Hiroki Nishikawa; Qiuyou Lian; Hiroyuki Tomiyama (IEEE Internet Things J., 2024)

Real-Time Performance Analysis for Multiple Neural Networks on Edge Devices. - Takumi Hikino; Hiroyuki Tomiyama (ICEIC, 2025)

Interval-Aware Scheduling of Surveillance Drones: Exact and Heuristic Approaches. - Kaito Mori; Hiroki Nishikawa; Hiroyuki Tomiyama (IEEE Access, 2025)