A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. - Shuou Nomura; Fumihiko Tachibana; Tetsuya Fujita; Chen Kong Teh; Hiroyuki Usui; Fumiyuki Yamane; Yukimasa Miyamoto; Chaiyasit Kumtornkittikul; Hiroyuki Hara; Takahiro Yamashita; Jun Tanabe; Masaru Uchiyama; et al. (ISSCC, 2008)

A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications. - Hui Xu; Jun Tanabe; Hiroyuki Usui; Soichiro Hosoda; Toru Sano; Kazumasa Yamamoto; Takeshi Kodaka; Nobuhiro Nonogaki; Nau Ozaki; Takashi Miyamori (VLSIC, 2012)

A near-future prediction method for low power consumption on a many-core processor. - Takeshi Kodaka; Akira Takeda; Shunsuke Sasaki; Akira Yokosawa; Toshiki Kizu; Takahiro Tokuyoshi; Hui Xu; Toru Sano; Hiroyuki Usui; Jun Tanabe; Takashi Miyamori; Nobu Matsumoto (DATE, 2013)

Development of low power many-core SoC for multimedia applications. - Takashi Miyamori; Hui Xu; Takeshi Kodaka; Hiroyuki Usui; Toru Sano; Jun Tanabe (DATE, 2013)

An evaluation of an energy efficient many-core SoC with parallelized face detection. - Hiroyuki Usui; Jun Tanabe; Toru Sano; Hui Xu; Takashi Miyamori (ASP-DAC, 2014)

Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters. - Takashi Miyamori; Hui Xu; Hiroyuki Usui; Soichiro Hosoda; Toru Sano; Kazumasa Yamamoto; Takeshi Kodaka; Nobuhiro Nonogaki; Nau Ozaki; Jun Tanabe (IEICE Trans. Electron., 2014)

SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators. - Hiroyuki Usui; Lavanya Subramanian; Kevin Kai-Wei Chang; Onur Mutlu (CoRR, 2015)

DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators. - Hiroyuki Usui; Lavanya Subramanian; Kevin Kai-Wei Chang; Onur Mutlu (ACM Trans. Archit. Code Optim., 2016)

Size distribution of urban blocks in the Tokyo Metropolitan Region: estimation by urban block density and road width on the basis of normative plane tessellation. - Hiroyuki Usui; Yasushi Asami (Int. J. Geogr. Inf. Sci., 2018)

Statistical distribution of building lot frontage: application for Tokyo downtown districts. - Hiroyuki Usui (J. Geogr. Syst., 2018)

Estimation of geometric route distance from its topological distance: application to narrow road networks in Tokyo. - Hiroyuki Usui (J. Geogr. Syst., 2018)

A bottom-up approach for delineating urban areas minimizing the connection cost of built clusters: Comparison with top-down-based densely inhabited districts. - Hiroyuki Usui (Comput. Environ. Urban Syst., 2019)

Variography and Morphometry for Classifying Building Centroids: Protocol, Data and Script. - Joan Perez; Alexandre Ornon; Hiroyuki Usui (ICCSA (4), 2020)

A comparison of neighbourhood relations based on ordinary Delaunay diagrams and area Delaunay diagrams: an application to define the neighbourhood relations of buildings. - Hiroyuki Usui; Akihiro Teraki; Kei-ichi Okunuki; Toshiaki Satoh (Int. J. Geogr. Inf. Sci., 2020)

A normative model to estimate the number of persons not social distancing in a 3D complex built space. - Hiroyuki Usui; Yasushi Asami; Ikuho Yamada (Int. J. Geogr. Inf. Sci., 2022)

Simulation of urban perforation after random vacant plot generation: application of the thinning point process. - Hiroyuki Usui (Int. J. Geogr. Inf. Sci., 2023)

Automatic measurement of building setbacks and streetscape widths and their spatial variability along streets and in plots: integration of streetscape skeletons and plot geometry. - Hiroyuki Usui (Int. J. Geogr. Inf. Sci., 2023)

Where Should Additional City Benches be Installed to Reduce Continuous Walking Distance? Comparison of Incrementally and Simultaneously Added Installations. - Hiroyuki Usui (Trans. GIS, 2024)