Synthesis for Testability by Sequential Redundancy Removal Using Retiming. - Hiroyuki Yotsuyanagi; Seiji Kajihara; Kozo Kinoshita (FTCS, 1995)

Resynthesis for sequential circuits designed with a specified initial state. - Hiroyuki Yotsuyanagi; Seiji Kajihara; Kozo Kinoshita (VTS, 1995)

Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement. - Hiroyuki Yotsuyanagi; Seiji Kajihara; Kozo Kinoshita (IEICE Trans. Inf. Syst., 1995)

Synthesis of Sequential Circuits by Redundancy Removal and Retiming. - Hiroyuki Yotsuyanagi; Seiji Kajihara; Kozo Kinoshita (J. Electron. Test., 1997)

Undetectable Fault Removal of Sequential Circuits Based on Unreachable States. - Hiroyuki Yotsuyanagi; Kozo Kinoshita (VTS, 1998)

Identification of Feedback Bridging Faults with Oscillation. - Masaki Hashizume; Hiroyuki Yotsuyanagi; Takeomi Tamesada (Asian Test Symposium, 1999)

High speed IDDQ test and its testability for process variation. - Masaki Hashizume; Hiroyuki Yotsuyanagi; Masahiro Ichimiya; Takeomi Tamesada; Masashi Takeda (Asian Test Symposium, 2000)

Testability Analysis of IDDQ Testing with Large Threshold Value. - Masaki Hashizume; Hiroyuki Yotsuyanagi; Takeomi Tamesada; Masashi Takeda (DFT, 2000)

CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application. - Masaki Hashizume; Masahiro Ichimiya; Hiroyuki Yotsuyanagi; Takeomi Tamesada (Asian Test Symposium, 2001)

IDDQ Sensing Technique for High Speed IDDQ Testing. - Teppei Takeda; Masaki Hashizume; Masahiro Ichimiya; Hiroyuki Yotsuyanagi; Yukiya Miura; Kozo Kinoshita (Asian Test Symposium, 2001)

Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States. - Hiroyuki Yotsuyanagi; Shinsuke Hata; Masaki Hashizume; Takeomi Tamesada (Asian Test Symposium, 2001)

CMOS open defect detection by supply current test. - Masaki Hashizume; Masahiro Ichimiya; Hiroyuki Yotsuyanagi; Takeomi Tamesada (DATE, 2001)

Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field. - Hiroyuki Yotsuyanagi; Masaki Hashizume; Taisuke Iwakiri; Masahiro Ichimiya; Takeomi Tamesada (DFT, 2001)

Test Time Reduction for I DDQ Testing by Arranging Test Vectors. - Hiroyuki Yotsuyanagi; Masaki Hashizume; Takeomi Tamesada (Asian Test Symposium, 2002)

Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits. - Masaki Hashizume; Masashi Sato; Hiroyuki Yotsuyanagi; Takeomi Tamesada (DELTA, 2002)

Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field. - Hiroyuki Yotsuyanagi; Masaki Hashizume; Taisuke Iwakiri; Masahiro Ichimiya; Takeomi Tamesada (DELTA, 2002)

A BIST Circuit for IDDQ Tests. - Masaki Hashizume; Teppei Takeda; Hiroyuki Yotsuyanagi; Takeomi Tamesada; Yukiya Miura; Kozo Kinoshita (Asian Test Symposium, 2003)

Reducing Scan Shifts Using Folding Scan Trees. - Hiroyuki Yotsuyanagi; Toshimasa Kuchii; Shigeki Nishikawa; Masaki Hashizume; Kozo Kinoshita (Asian Test Symposium, 2003)

I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment. - Masaki Hashizume; Daisuke Yoneda; Hiroyuki Yotsuyanagi; Tetsuo Tada; Takeshi Koyama; Ikuro Morita; Takeomi Tamesada (Asian Test Symposium, 2004)

A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits. - Daisuke Ezaki; Masaki Hashizume; Hiroyuki Yotsuyanagi; Takeomi Tamesada (DELTA, 2004)

CMOS Open Fault Detection by Appearance Time of Switching Supply Current. - Masaki Hashizume; Tetsuo Akita; Hiroyuki Yotsuyanagi; Takeomi Tamesada (DELTA, 2004)

Practical Fault Coverage of Supply Current Tests for Bipolar ICs. - Isao Tsukimoto; Masaki Hashizume; Hiroyuki Yotsuyanagi; Takeomi Tamesada (DELTA, 2004)

On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure. - Hiroyuki Yotsuyanagi; Toshimasa Kuchii; Shigeki Nishikawa; Masaki Hashizume; Kozo Kinoshita (DELTA, 2004)

Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits. - Masaki Hashizume; Hiroyuki Yotsuyanagi; Takeomi Tamesada (IEICE Trans. Inf. Syst., 2004)

Test Sequence Generation for Test Time Reduction of IDDQ Testing. - Hiroyuki Yotsuyanagi; Masaki Hashizume; Takeomi Tamesada (IEICE Trans. Inf. Syst., 2004)

A test circuit for pin shorts generating oscillation in CMOS logic circuits. - Masahiro Ichimiya; Masaki Hashizume; Hiroyuki Yotsuyanagi; Takeomi Tamesada (Syst. Comput. Jpn., 2004)

Electric field for detecting open leads in CMOS logic circuits by supply current testing. - Masaki Hashizume; Masahiro Ichimiya; Hiroyuki Yotsuyanagi; Takeomi Tamesada (ISCAS (3), 2005)

Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. - Hiroyuki Yotsuyanagi; Toshimasa Kuchii; Shigeki Nishikawa; Masaki Hashizume; Kozo Kinoshita (J. Electron. Test., 2005)

A BIC Sensor Capable of Adjusting IDDQ Limit in Tests. - Masato Nakanishi; Masaki Hashizume; Hiroyuki Yotsuyanagi; Yukiya Miura (ATS, 2006)

Current Testable Design of Resistor String DACs. - Masaki Hashizume; Tomomi Nishida; Hiroyuki Yotsuyanagi; Takeomi Tamesada; Yukiya Miura (DELTA, 2006)

Current Testable Design of Resistor String DACs. - Masaki Hashizume; Yutaka Hata; Tomomi Nishida; Hiroyuki Yotsuyanagi; Yukiya Miura (ATS, 2007)

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines. - Hiroshi Takahashi; Yoshinobu Higami; Shuhei Kadoyama; Takashi Aikyo; Yuzo Takamatsu; Koji Yamazaki; Toshiyuki Tsutsumi; Hiroyuki Yotsuyanagi; Masaki Hashizume (ATS, 2007)

Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. - Hiroshi Takahashi; Yoshinobu Higami; Toru Kikkawa; Takashi Aikyo; Yuzo Takamatsu; Hiroyuki Yotsuyanagi; Masaki Hashizume (DFT, 2007)

New Class of Tests for Open Faults with Considering Adjacent Lines. - Hiroshi Takahashi; Yoshinobu Higami; Yuzo Takamatsu; Koji Yamazaki; Toshiyuki Tsutsumi; Hiroyuki Yotsuyanagi; Masaki Hashizume (Asian Test Symposium, 2009)

A Novel Approach for Improving the Quality of Open Fault Diagnosis. - Koji Yamazaki; Toshiyuki Tsutsumi; Hiroshi Takahashi; Yoshinobu Higami; Takashi Aikyo; Yuzo Takamatsu; Hiroyuki Yotsuyanagi; Masaki Hashizume (VLSI Design, 2009)

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. - Hiroyuki Yotsuyanagi; Masaki Hashizume; Toshiyuki Tsutsumi; Koji Yamazaki; Takashi Aikyo; Yoshinobu Higami; Hiroshi Takahashi; Yuzo Takamatsu (VLSI Design, 2009)

Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code. - Masashi Ishikawa; Hiroyuki Yotsuyanagi; Masaki Hashizume (Asian Test Symposium, 2010)

Current-based testable design of level shifters in liquid crystal display drivers. - Masaki Hashizume; Kazuya Nakaminami; Hiroyuki Yotsuyanagi; Yukinori Nakajima; Kozo Kinoshita (ETS, 2010)

Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops. - Hiroyuki Yotsuyanagi; Masayuki Yamamoto; Masaki Hashizume (IEICE Trans. Inf. Syst., 2010)

Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture. - Tomoaki Konishi; Hiroyuki Yotsuyanagi; Masaki Hashizume (3DIC, 2011)

A built-in test circuit for open defects at interconnects between dies in 3D ICs. - Widianto; Hiroyuki Yotsuyanagi; Akira Ono; Masao Takagi; Masaki Hashizume (3DIC, 2011)

A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing. - Hiroyuki Yotsuyanagi; Hiroyuki Makimoto; Masaki Hashizume (Asian Test Symposium, 2011)

A supply current testable register string DAC of decoder type. - Masaki Hashizume; Yutaka Hata; Hiroyuki Yotsuyanagi; Yukiya Miura (ISCIT, 2011)

Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs. - Masaki Hashizume; Tomoaki Konishi; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (Asian Test Symposium, 2013)

SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines. - Jun Yamashita; Hiroyuki Yotsuyanagi; Masaki Hashizume; Kozo Kinoshita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan. - Hiroyuki Yotsuyanagi; Hiroyuki Makimoto; Takanobu Nimiya; Masaki Hashizume (IEICE Trans. Inf. Syst., 2013)

A built-in supply current test circuit for electrical interconnect tests of 3D ICs. - Masaki Hashizume; Shoichi Umezu; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (3DIC, 2014)

Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit. - Kosuke Nanbara; Akihiro Odoriba; Masaki Hashizume; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (3DIC, 2015)

Electrical interconnect test method of 3D ICs by injected charge volume. - Daisuke Suga; Masaki Hashizume; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (3DIC, 2015)

On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs. - Hiroyuki Yotsuyanagi; Akihiro Fujiwara; Masaki Hashizume (3DIC, 2015)

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs. - Widianto; Masaki Hashizume; Shohei Suenaga; Hiroyuki Yotsuyanagi; Akira Ono; Shyue-Kung Lu; Zvi Roth (IEICE Trans. Inf. Syst., 2016)

Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs. - Ayumu Kambara; Hiroyuki Yotsuyanagi; Daichi Miyoshi; Masaki Hashizume; Shyue-Kung Lu (ATS, 2017)

Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories. - Shyue-Kung Lu; Shu-Chi Yu; Masaki Hashizume; Hiroyuki Yotsuyanagi (ATS, 2017)

A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type. - Michiya Kanda; Masaki Hashizume; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (DFT, 2017)

On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects. - Yuuya Ohama; Hiroyuki Yotsuyanagi; Masaki Hashizume; Yoshinobu Higami; Hiroshi Takahashi (ISCIT, 2017)

A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume. - Kouhei Ohtani; Naho Osato; Masaki Hashizume; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (ISCIT, 2017)

Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines. - Hiroyuki Yotsuyanagi; Kotaro Ise; Masaki Hashizume; Yoshinobu Higami; Hiroshi Takahashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design. - Satoshi Hirai; Hiroyuki Yotsuyanagi; Masaki Hashizume (ATS, 2018)

A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification. - Toshinori Hosokawa; Morito Niseki; Masayoshi Yoshimura; Hiroshi Yamazaki; Masayuki Arai; Hiroyuki Yotsuyanagi; Masaki Hashizume (IOLTS, 2018)

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs. - Fara Ashikin; Masaki Hashizume; Hiroyuki Yotsuyanagi; Shyue-Kung Lu; Zvi Roth (IEICE Trans. Inf. Syst., 2018)

On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection. - Toshiaki Satoh; Hiroyuki Yotsuyanagi; Masaki Hashizume (3DIC, 2019)

Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes. - Hanna Soneda; Masaki Hashizume; Hiroyuki Yotsuyanagi; Shyue-Kung Lu (3DIC, 2019)

On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC. - Shuya Kikuchi; Hiroyuki Yotsuyanagi; Masaki Hashizume (ITC-Asia, 2019)

Fault-Aware Dependability Enhancement Techniques for Flash Memories. - Shyue-Kung Lu; Shu-Chi Yu; Chun-Lung Hsu; Chi-Tien Sun; Masaki Hashizume; Hiroyuki Yotsuyanagi (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators. - Masao Ohmatsu; Yuto Ohtera; Yuki Ikiri; Hiroyuki Yotsuyanagi; Shyue-Kung Lu; Masaki Hashizume (ATS, 2022)

On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults. - Shogo Tokai; Daichi Akamatsu; Hiroyuki Yotsuyanagi; Masaki Hashizume (ITC-Asia, 2023)

Detectability of Resistive Open Defects with Analog Relaxation Oscillators Under Unit-to-Unit Variations of Dies. - Yuya Yamahashi; Yuto Ohtera; Hiroyuki Yotsuyanagi; Shyue-Kung Lu; Masaki Hashizume (3DIC, 2024)

Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs. - Senling Wang; Shaoqi Wei; Hisashi Okamoto; Tatusya Nishikawa; Hiroshi Kai; Yoshinobu Higami; Hiroyuki Yotsuyanagi; Ruijun Ma; Tianming Ni; Hiroshi Takahashi; Xiaoqing Wen (ITC-Asia, 2024)