Design of high speed MOS multiplier and divider using redundant binary representation. - Shigeo Kuninobu; Tamotsu Nishiyama; Hisakazu Edamatsu; Takashi Taniguchi; Naofumi Takagi (IEEE Symposium on Computer Arithmetic, 1987)

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor. - Jito Miyake; Todhinoti Maeda; Yoshito Nishimichi; Johi Katsura; Takashi Taniguchi; Seihi Yamaguchi; Hisakazu Edamatsu; Shigeru Watari; Yoshiyuko Takagi; Kazuhiko Tsuji; Shigeo Kuninobu; Steve Cox; et al. (IEEE J. Solid State Circuits, 1990)

Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation. - Hideyuki Kabuo; Takashi Taniguchi; Akira Miyoshi; Hitoshi Yamashita; Miki Urano; Hisakazu Edamatsu; Shigeo Kuninobu (IEEE Trans. Computers, 1994)

Design Methodologies for consumer-use video signal processing LSIs. - Hisakazu Edamatsu; Satoshi Ikawa; Katsuya Hasegawa (DAC, 1996)

Pre-layout Delay Calculation Specification for CMOS ASIC Libraries. - Hisakazu Edamatsu; Katsumi Homma; Masaru Kakimoto; Yutaka Koike; Kinya Tabuchi (ASP-DAC, 1998)