A 100-mega-access per second matching memory for a data-driven microprocessor. - Hidehiro Takata; Shinji Komori; Toshiyuki Tamura; Fumiyasu Asai; Hisakazu Sato; Takio Ohno; Takeshi Tokuda; Hiroki Nishikawa; Hirofumi Terada (IEEE J. Solid State Circuits, 1990)

A Data-Driven Architecture for Distributed Parallel Processing. - Toshiyuki Tamura; Shinji Komori; Fumiyasu Asai; Hirono Tsubota; Hisakazu Sato; Hidehiro Takata; Yoshihiro Seguchi; Takeshi Tokuda; Hiroaki Terada (ICCD, 1991)

A dual-issue RISC processor for multimedia signal processing. - Hisakazu Sato; Edgar Holmann; Toyohiko Yoshida; Masahito Matsuo; Toru Kengaku (ICASSP, 1997)

A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores. - Satoshi Kumaki; Tetsuya Matsumura; Kamya Ishihara; Hiroshi Segawa; Kiyofumi Kawamoto; Hideo Ohira; Toshiaki Shimada; Hidenori Sato; Takashi Hattori; Tetsuro Wada; Hiroshi Honma; Tetsuya Watanabe; et al. (CICC, 1999)

A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor. - Atsushi Mohri; Akira Yamada 005; Y. Yoshida; Hisakazu Sato; Hidehiro Takata; K. Nakakimura; M. Hashizume; Y. Shimotsuma; K. Tsuchihashi (IEEE J. Solid State Circuits, 1999)

The D30V/MPEG multimedia processor. - Hidehiro Takata; Tetsuya Watanabe; Tetsuo Nakajima; Takashi Takagaki; Hisakazu Sato; Atsushi Mohri; Akira Yamada 005; Toshiki Kanamoto; Yoshio Matsuda; Shuhei Iwade; Yasutaka Horiba (IEEE Micro, 1999)