A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM. - Kazuyuki Nakamura; Takashi Oguri; Takao Atsumo; Masahide Takada; Atsushi Ikemoto; Hisamitsu Suzuki; Tadashi Nishigori; Tohru Yamazaki (IEEE J. Solid State Circuits, 1992)

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator. - Kazuyuki Nakamura; Shigeru Kuhara; Tohru Kimura; Masahide Takada; Hisamitsu Suzuki; Hiroshi Yoshida; Tohru Yamazaki (IEEE J. Solid State Circuits, 1994)

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM. - Hideo Toyoshima; Shigeru Kuhara; Koichi Takeda 001; Kazuyuki Nakamura; Hiloshi Okamura; Masahide Takada; Hisamitsu Suzuki; Hiroshi Yoshida; Tohru Yamazaki (IEEE J. Solid State Circuits, 1996)

The direct skew detect synchronous mirror delay (Direct SMD) for ASICs. - Takanori Saeki; Koichiro Minami; Hiroshi Yoshida; Hisamitsu Suzuki (CICC, 1998)

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications. - Muneo Fukaishi; Satoshi Nakamura; Akio Tajima; Yasushi Kinoshita; Yoshihiko Suemura; Hisamitsu Suzuki; Toshiro Itani; Hidenobu Miyamoto; Naoya Henmi; Tohru Yamazaki; Michio Yotsuyanagi (IEEE J. Solid State Circuits, 1999)

A direct-skew-detect synchronous mirror delay for application-specific integrated circuits. - Takanori Saeki; Koichiro Minami; Hiroshi Yoshida; Hisamitsu Suzuki (IEEE J. Solid State Circuits, 1999)