A 100-MHz 4-Mb cache DRAM with fast copy-back scheme. - Katsumi Dosaka; Yasuhiro Konishi; Kouji Hayano; Katsumitsu Himukashi; Akira Yamazaki; Hisashi Iwamoto; Masaki Kumanoya; Hisanori Hamano; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1992)

Deterministic High Density Packet-Buffer System for Low Cost Network Systems. - Hisashi Iwamoto; Yuji Yano; Yasuto Kuroda; Koji Yamamoto 002; Shingo Ata; Kazunari Inoue (AINA, 2012)

A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application. - Yasuto Kuroda; Yuji Yano; Hisashi Iwamoto; Koji Yamamoto 002; Kazunari Inoue; Masahiro Suzuki (CICC, 2012)

A slice structure using the management of network traffic prediction for green IT. - Yuji Yano; Hisashi Iwamoto; Yasuto Kuroda; Shiro Ohtani; Shingo Ata; Kazunari Inoue (HPSR, 2012)

2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving. - Kenzo Okuda; Shingo Ata; Yasuto Kuroda; Yuji Yano; Hisashi Iwamoto; Kazunari Inoue; Ikuo Oka (CCNC, 2013)

Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS. - Hisashi Iwamoto; Yuji Yano; Yasuto Kuroda; Koji Yamamoto 002; Shingo Ata; Kazunari Inoue (IEICE Trans. Commun., 2013)

A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application. - Hisashi Iwamoto; Yuji Yano; Yasuto Kuroda; Koji Yamamoto 002; Kazunari Inoue; Ikuo Oka (IEICE Trans. Electron., 2013)

A study on micro level traffic prediction for energy-aware routers. - Sou Koyano; Shingo Ata; Hisashi Iwamoto; Yuji Yano; Yasuto Kuroda; Kazunari Inoue; Ikuo Oka (ACM SIGOPS Oper. Syst. Rev., 2013)

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Hisashi Iwamoto; Yasuhiro Terao (IEICE Trans. Inf. Syst., 2015)

Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure. - Masami Nawa; Kenzo Okuda; Shingo Ata; Yasuto Kuroda; Yuji Yano; Hisashi Iwamoto; Kazunari Inoue; Ikuo Oka (CCNC, 2016)

A memory-based realization of a binarized deep convolutional neural network. - Hiroki Nakahara; Haruyoshi Yonekawa; Tsutomu Sasao; Hisashi Iwamoto; Masato Motomura (FPT, 2016)

LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification. - Hiroki Nakahara; Tsutomu Sasao; Hisashi Iwamoto; Munehiro Matsuura (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k). - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Hisashi Iwamoto (J. Multiple Valued Log. Soft Comput., 2016)

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). - Hiroki Nakahara; Haruyoshi Yonekawa; Hisashi Iwamoto; Masato Motomura (FPGA, 2017)

28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System. - Yuji Yano; Hisashi Iwamoto; Takuma Yoshimura; Yoshihiro Nishida; Tatsuya Mori; Kiyotaka Komoku; Hidekuni Takao; Kazutami Arimoto (VLSI-DAT, 2022)