A 1.3GHz fifth generation SPARC64 microprocessor. - Hisashige Ando; Yuuji Yoshida; Aiichiro Inoue; Itsumi Sugiyama; Takeo Asakawa; Kuniki Morita; Toshiyuki Muta; Tsuyoshi Motokurumada; Seishi Okada; Hideo Yamashita; Yoshihiko Satsukawa; Akihiko Konmoto; et al. (DAC, 2003)

A 1.3-GHz fifth-generation SPARC64 microprocessor. - Hisashige Ando; Yuuji Yoshida; Aiichiro Inoue; Itsumi Sugiyama; Takeo Asakawa; Kuniki Morita; Toshiyuki Muta; Tsuyoshi Motokurumada; Seishi Okada; Hideo Yamashita; Yoshihiko Satsukawa; Akihiko Konmoto; et al. (IEEE J. Solid State Circuits, 2003)

A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing. - Hisashige Ando; Nestoras Tzartzanis; William W. Walker (IEEE Trans. Very Large Scale Integr. Syst., 2005)

High-Speed Interconnect for a Multiprocessor Server Using Over 1Tb/s Crossbar. - Jun Yamada; Hiroyuki Adachi; Yutaka Mori; Akihiko Harada; Seishi Okada; Hisashige Ando (ISSCC, 2006)

A Case Study: Energy Efficient High Throughput Chip Multi-Processor Using Reduced-complexity Cores for Transaction Processing Workload. - Hisashige Ando; Akira Asato; Motoyuki Kawaba; Hideki Okawara; William W. Walker (Inf. Media Technol., 2006)

Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor. - Hisashige Ando; Ryuji Kan; Yoshiharu Tosaka; Keiji Takahisa; Kichiji Hatanaka (DSN, 2008)

Performance prediction of large-scale parallell system and application using macro-level simulation. - Ryutaro Susukita; Hisashige Ando; Mutsumi Aoyagi; Hiroaki Honda; Yuichi Inadomi; Koji Inoue; Shigeru Ishizuki; Yasunori Kimura; Hidemi Komatsu; Motoyoshi Kurokawa; Kazuaki J. Murakami; Hidetomo Shibamura; et al. (SC, 2008)

NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers. - Hideki Miwa; Ryutaro Susukita; Hidetomo Shibamura; Tomoya Hirao; Jun Maki; Makoto Yoshida; Takayuki Kando; Yuichiro Ajima; Ikuo Miyoshi; Toshiyuki Shimizu; Yuji Oinaga; Hisashige Ando; et al. (IEICE Trans. Inf. Syst., 2011)