11 GHz UGBW Op-amp with feed-forward compensation technique. - Hitesh Shrimali; Shouri Chatterjee (ISCAS, 2011)

Third order harmonic cancellation technique for a parametric amplifier. - Hitesh Shrimali; Shouri Chatterjee (ISCAS, 2011)

Distortion Analysis of a Three-Terminal MOS-Based Discrete-Time Parametric Amplifier. - Hitesh Shrimali; Shouri Chatterjee (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

The start-up circuit for a low voltage bandgap reference. - Hitesh Shrimali; Valentino Liberali (ICECS, 2014)

A technique to linearize the discrete-time parametric amplifier. - Hitesh Shrimali; Shouri Chatterjee (Microelectron. J., 2015)

The pole-zero doublet: A cascode operational amplifier with cross coupled capacitor. - Ashish Joshi; Indu Yadav; Satinder K. Sharma; Hitesh Shrimali (MWSCAS, 2016)

Nonlinear modeling and analysis of buck converter using volterra series. - Hitesh Shrimali; Vijender Kumar Sharma; Jai Narayan Tripathi; Rakesh Malik (ICECS, 2017)

Distortion analysis for a DC-DC buck converter. - Vijender Kumar Sharma; Hitesh Shrimali; Jai Narayan Tripathi; Rakesh Malik (ISOCC, 2017)

Systematic design approach for a gain boosted telescopic OTA with cross-coupled capacitor. - Ashish Joshi; Hitesh Shrimali; Satinder K. Sharma (IET Circuits Devices Syst., 2017)

The Capacitively Coupled Chopper Stabilized Amplifier with a DTPA based Demodulator. - Ashish Joshi; Hitesh Shrimali; Satinder K. Sharma (ISCAS, 2018)

Design of a Third Order Butterworth Gm-C Filter for EEG Signal Detection Application. - Ankita Deo; Sumit K. Pandey; Ashish Joshi; Satinder K. Sharma; Hitesh Shrimali (MIXDES, 2018)

Energy Efficient Bootstrapped Driver for a Particle Detector in 180 nm SOI Technology. - Saurabh Dhiman; Indu Yadav; Hitesh Shrimali (APCCAS, 2019)

An Ultra-Fast Parallel Prefix Adder. - Kumar Sambhav Pandey; B. Dinesh Kumar 001; Neeraj Goel; Hitesh Shrimali (ARITH, 2019)

Design of HV-CMOS Detectors in BCD Technology with Noise and Crosstalk Measurements. - Indu Yadav; Ashish Joshi; Ettore Ruscino; Valentino Liberali; Attilio Andreazza; Hitesh Shrimali (ICECS, 2019)

A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS. - B. Dinesh Kumar 001; Hitesh Shrimali; Navneet Gupta (ISCAS, 2019)

Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator. - Vijender Kumar Sharma; B. Dinesh Kumar 001; Muhammed Suhail Illikkal; Jai Narayan Tripathi; Navneet Gupta; Hitesh Shrimali (ISCAS, 2019)

Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm Process. - Indu Yadav; Ashish Joshi; Ettore Ruscino; Valentino Liberali; Attilio Andreazza; Hitesh Shrimali (VLSID, 2019)

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers. - Jai Narayan Tripathi; Muhammed Suhail Illikkal; Hitesh Shrimali; Ramachandra Achar (IEEE Access, 2019)

Design and Analysis of a Low PSIJ, Energy Efficient Bootstrapped Driver for Space Application. - Saurabh Dhiman; Vijender Kumar Sharma; Hitesh Shrimali (ISCAS, 2020)

Reduced switching mode for SAR ADCs: analysis and design of SAR A-to-D algorithm with periodic standby mode circuit components. - Ashish Joshi; Hitesh Shrimali; Satinder K. Sharma (IET Circuits Devices Syst., 2020)

Design of hybrid flash-SAR ADC using an inverter based comparator in 28 nm CMOS. - B. Dinesh Kumar 001; Sumit K. Pandey; Navneet Gupta; Hitesh Shrimali (Microelectron. J., 2020)

Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix. - Vijender Kumar Sharma; Jai Narayan Tripathi; Hitesh Shrimali (IEEE Open J. Circuits Syst., 2020)

A Discrete-Time MOS Parametric Amplifier-Based Chopped Signal Demodulator. - Ashish Joshi; Hitesh Shrimali; Satinder K. Sharma (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Design of CMOS Device Process Sensor in 28 nm FD-SOI with 2 % of Frequency Spread. - Gowtham Peringattu Kalarikkal; Rohit Goel; Hitesh Shrimali (ICECS, 2021)

A Low-Power Quadrature LC-Oscillator Using Core-and-Coupling Current-Reuse. - B. Dinesh Kumar 001; Hitesh Shrimali; Nagarjuna Nallam (ISCAS, 2021)

Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC. - Navneet Gupta; Hitesh Shrimali; Adam Makosiej; Andrei Vladimirescu; Amara Amara (MWSCAS, 2021)

Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters due to Periodic Fluctuations. - Puneet Arora; Jai Narayan Tripathi; Hitesh Shrimali (NEWCAS, 2021)

Digitally Assisted Secondary Switch-and-Compare Technique for a SAR ADC. - Ashish Joshi; Hitesh Shrimali; Satinder K. Sharma (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters. - Muhammed Suhail Illikkal; Jai Narayan Tripathi; Vijender Kumar Sharma; Hitesh Shrimali; Ramachandra Achar (IEEE Access, 2022)

Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations. - Kumar Sambhav Pandey; Hitesh Shrimali (IEEE Access, 2022)

Design and implementation of a second order PLL based frequency synthesizer for implantable medical devices. - B. Dinesh Kumar 001; Hitesh Shrimali (Integr., 2022)

Fully Monolithic 1A Thermoelectric Cooler Controller with 90% Efficiency. - Sowmyashree S; Hitesh Shrimali (ICECS, 2023)

A Low Noise Bandgap Reference with 0.89 V Vref, 0.88 μVrms noise and 80 dB of PSRR. - Sowmyashree S; Hitesh Shrimali (VLSID, 2023)

A 5.4mW 12GHz Quadrature VCO using current reusing technique in 28nm CMOS technology. - Zahid Rashid Sheikh; Taranveer Kaur; Rajasekhar Nagulapalli; Hitesh Shrimali; Mahendra Sakare (ICCCNT, 2024)

A 12.7 Bit Accurate and 5.3nJ·µV2·ns Comparator with Dynamic-cum-Body Bias Technique in SOI. - Saurabh Dhiman; Hitesh Shrimali (ISCAS, 2024)

A 66dBΩ 5 GHz and 44.88 √Hz/(pA·pW) Inductorless TIA in 65 nm CMOS. - Azhar Yaseen N. J; Shivdeep; Sahil Sharma; Hitesh Shrimali; Devarshi Mrinal Das (MIXDES, 2024)

An On-chip Thermoelectric Cooler Controller With Improved Driving Current of 2 A at 0.5 Ω Load. - Sowmyashree S; Hitesh Shrimali (VLSID, 2024)

On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity. - Saurabh Dhiman; Hitesh Shrimali (Integr., 2024)

Corrigendum to "On minimizing charge injection error using multi-dummy switches with enhanced linearity" [Integration volume 97 (2024) 102175]. - Saurabh Dhiman; Hitesh Shrimali (Integr., 2024)