A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor. - Kazumasa Suzuki; Masakazu Yamashina; Takashi Nakayama; Masanori Izumikawa; Masahiro Nomura; Hiroyuki Igura; Hideki Heiuchi; Junichi Goto; Toshiaki Inoue; Youichi Koseki; Hitoshi Abiko; Kazuhiro Okabe; et al. (IEEE J. Solid State Circuits, 1994)

A GHz MOS adaptive pipeline technique using MOS current-mode logic. - Masayuki Mizuno; Masakazu Yamashina; Koichiro Furuta; Hiroyuki Igura; Hitoshi Abiko; Kazuhiro Okabe; Atsuki Ono; Hachiro Yamada (IEEE J. Solid State Circuits, 1996)