A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design. - Kenichi Imamiya; Jun-ichi Miyamoto; Shigeru Atsumi; Nobuaki Ohtsuka; Yukinori Muroya; Toshiyuki Sako; Masao Higashino; Yumiko Iyama; Seiichi Mori; Yoichi Ohshima; Hitoshi Araki; Yukio Kaneko; et al. (IEEE J. Solid State Circuits, 1990)

A 16-ns 1-Mb CMOS EPROM. - Masao Kuriyama; Shigeru Atsumi; Ken-ichi Imamiya; Yumiko Iyama; Naohiro Matsukawa; Hitoshi Araki; Kazuhito Narita; Kazunori Masuda; Sumio Tanaka (IEEE J. Solid State Circuits, 1990)

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM. - Yoshihisa Iwata; Ken-ichi Imamiya; Yoshihisa Sugiura; Hiroshi Nakamura; Hideko Oodaira; Masaki Momodomi; Yasuo Itoh; Toshiharu Watanabe; Hitoshi Araki; Kazuhito Narita; Kazunori Masuda; Junichi Miyamoto (IEEE J. Solid State Circuits, 1995)