An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller. - Koichi Seki; Hitoshi Kume; Yuzuru Ohji; Takashi Kobayashi 002; Atushi Hiraiwa; Takeshi Nishida; Takeshi Wada; Kazuhiro Komori; Kazuto Izawa; Toshiaki Nishimoto; Yasuroh Kubota; Kazuyoshi Shoji (IEEE J. Solid State Circuits, 1990)

A Case History Analysis of Software Error Cause-Effect Relationships. - Takeshi Nakajo; Hitoshi Kume (IEEE Trans. Software Eng., 1991)

A test-path determination method based on define-use chains: Test conditions and program fault overlooks. - Takeshi Nakajo; Ichiro Yamaguchi; Hitoshi Kume (Syst. Comput. Jpn., 1993)

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories. - Takayuki Kawahara; Takashi Kobayashi 002; Yusuke Jyouno; Syun-ichi Saeki; Naoki Miyamoto; T. Adachi; Masataka Kato; Akihiko Sato; J. Yugami; Hitoshi Kume; Katsutaka Kimura (IEEE J. Solid State Circuits, 1996)

A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications. - Atsushi Nozoe; Hiroaki Kotani; Tetsuya Tsujikawa; Keiichi Yoshida; Kazunori Furusawa; Masataka Kato; Toshiaki Nishimoto; Hitoshi Kume; Hideaki Kurata; Naoki Miyamoto; Shoji Kubono; Michitaro Kanamitsu; et al. (IEEE J. Solid State Circuits, 1999)

A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology. - Hideaki Kurata; Satoshi Noda; Yoshitaka Sasago; Kazuo Otsuga; Tsuyoshi Arigane; Tetsufumi Kawamura; Takashi Kobayashi 002; Hitoshi Kume; Kazuki Homma; Teruhiko Ito; Yoshinori Sakamoto; Masahiro Shimizu; et al. (IEICE Trans. Electron., 2007)