A 23-ns 1-Mb BiCMOS DRAM. - Goro Kitsukawa; Kazumasa Yanagisawa; Yutaka Kobayashi; Yoshitaka Kinoshita; Tatsuyuki Ohta; Tetsu Udagawa; Hitoshi Miwa; Hiroyuki Miyazawa; Yoshiki Kawajiri; Yoshiaki Ouchi; Hiromi Tsukada; Tetsuro Matsumoto; et al. (IEEE J. Solid State Circuits, 1990)

Storage Enhancement Techniques for Digital Memory Based, Analog Computational Engines. - Hitoshi Miwa; Kewei Yang 003; Philippe O. Pouliquen; Nagendra Kumar 006; Andreas G. Andreou (ISCAS, 1994)

11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology. - Ryuji Yamashita; Sagar Magia; Tsutomu Higuchi; Kazuhide Yoneya; Toshio Yamamura; Hiroyuki Mizukoshi; Shingo Zaitsu; Minoru Yamashita; Shunichi Toyama; Norihiro Kamae; Juan Lee; Shuo Chen; et al. (ISSCC, 2017)

A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology. - Chang Hua Siau; Kwang-Ho Kim; Seungpil Lee; Katsuaki Isobe; Noboru Shibata; Kapil Verma; Takuya Ariki; Jason Li 001; Jong Yuh; Anirudh Amarnath; Qui Nguyen; Ohwon Kwon; et al. (ISSCC, 2019)