A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors. - Hitoshi Okamura; Hideo Toyoshima; Koichi Takeda; Takashi Oguri; Satoshi Nakamura; Masahide Takada; Kiyotaka Imai; Yasushi Kinoshita; Hiroshi Yoshida; Tom Yamazaki (IEEE J. Solid State Circuits, 1995)

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump. - Hitoshi Okamura; Takao Atsumo; Koichi Takeda; Masahide Takada; Kiyotaka Imai; Yasushi Kinoshita; Tom Yamazaki (IEEE J. Solid State Circuits, 1996)

Development of a Bedside Wellness System. - Mieko Ohsuga; Yoko Tatsuno; Futomi Shimono; Kousuke Hirasawa; Hiroshi Oyama 001; Hitoshi Okamura (Cyberpsychology Behav. Soc. Netw., 1998)

Quantification of Circadian Rhythms in Single Cells. - Pål O. Westermark; David K. Welsh; Hitoshi Okamura; Hanspeter Herzel (PLoS Comput. Biol., 2009)