A CMOS bandgap reference circuit with sub-1-V operation. - Hironori Banba; Hitoshi Shiga; Akira Umezawa; Takeshi Miyaba; Toru Tanzawa; Shigeru Atsumi; Koji Sakui (IEEE J. Solid State Circuits, 1999)

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. - Shigeru Atsumi; Akira Umezawa; Toru Tanzawa; Tadayuki Taura; Hitoshi Shiga; Yoshinori Takano; Takeshi Miyaba; Michiharu Matsui; Hiroshi Watanabe; Kazuaki Isobe; Shota Kitamura; Seiji Yamada; et al. (IEEE J. Solid State Circuits, 2000)

Wordline voltage generating system for low-power low-voltage flash memories. - Toru Tanzawa; Akira Umezawa; Masao Kuriyama; Tadayuki Taura; Hironori Banba; Takeshi Miyaba; Hitoshi Shiga; Yoshinori Takano; Shigeru Atsumi (IEEE J. Solid State Circuits, 2001)

A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller. - Toru Tanzawa; Akira Umezawa; Tadayuki Taura; Hitoshi Shiga; Tokumasa Hara; Yoshinori Takano; Takeshi Miyaba; Naoya Tokiwa; Kentaro Watanabe; Hiroshi Watanabe; Kazunori Masuda; Kiyomi Naruke; et al. (IEEE J. Solid State Circuits, 2002)

A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput. - Ken Takeuchi; Yasushi Kameda; Susumu Fujimura; Hiroyuki Otake; Koji Hosono; Hitoshi Shiga; Yoshihisa Watanabe; Takuya Futatsuyama; Yoshihiko Shindo; Masatsugu Kojima; Makoto Iwai; Masanobu Shirakawa; et al. (ISSCC, 2006)

A 56-nm CMOS 99-mm2 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput. - Ken Takeuchi; Yasushi Kameda; Susumu Fujimura; Hiroyuki Otake; Koji Hosono; Hitoshi Shiga; Yoshihisa Watanabe; Takuya Futatsuyama; Yoshihiko Shindo; Masatsugu Kojima; Makoto Iwai; Masanobu Shirakawa; et al. (IEEE J. Solid State Circuits, 2007)

A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate. - Yan Li; Seungpil Lee; Yupin Fong; Feng Pan; Tien-Chien Kuo; Jong Park; Tapan Samaddar; Hao Nguyen; Man Mui; Khin Htoo; Teruhiko Kamei; Masaaki Higashitani; et al. (ISSCC, 2008)

A 113mm2 32Gb 3b/cell NAND flash memory. - Takuya Futatsuyama; Norihiro Fujita; Naoya Tokiwa; Yoshihiko Shindo; Toshiaki Edahiro; Teruhiko Kamei; Hiroaki Nasu; Makoto Iwai; Koji Kato; Yasuyuki Fukuda; Naoaki Kanagawa; Naofumi Abiko; et al. (ISSCC, 2009)

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate. - Yan Li; Seungpil Lee; Yupin Fong; Feng Pan; Tien-Chien Kuo; Jongmin Park; Tapan Samaddar; Hao Nguyen; Man Mui; Khin Htoo; Teruhiko Kamei; Masaaki Higashitani; et al. (IEEE J. Solid State Circuits, 2009)

A 151mm2 64Gb MLC NAND flash memory in 24nm CMOS technology. - Koichi Fukuda; Yoshihisa Watanabe; Eiichi Makino; Koichi Kawakami; Jumpei Sato; Teruo Takagiwa; Naoaki Kanagawa; Hitoshi Shiga; Naoya Tokiwa; Yoshihiko Shindo; Toshiaki Edahiro; Takeshi Ogawa; et al. (ISSCC, 2011)

A 151-mm2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology. - Koichi Fukuda; Yoshihisa Watanabe; Eiichi Makino; Koichi Kawakami; Jumpei Sato; Teruo Takagiwa; Naoaki Kanagawa; Hitoshi Shiga; Naoya Tokiwa; Yoshihiko Shindo; Takeshi Ogawa; Toshiaki Edahiro; et al. (IEEE J. Solid State Circuits, 2012)

Crossed Bit Line (CBL) Architecture in 3D Flash Memory CMOS Directly Bonded to Array (CBA) Structure. - Hiroshi Maejima; Katsuaki Isobe; N. Okada; Masaki Unno; T. Hashimoto; Tetsuaki Utsumi; T. Hisada; K. Maruyama; Toshiyuki Kouchi; T. Kotani; Hitoshi Shiga; O. Kwon; et al. (IMW, 2025)