A submicrometer MOS transistor I-V model for circuit simulation. - Hiroo Masuda; Jun'ichi Mano; Ryuichi Ikematsu; Hitoshi Sugihara; Yukio Aoki (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance. - Takashi Sato 001; Toshiki Kanamoto; Saiko Kobayashi; Nobuhiko Goto; Takao Sato; Hitoshi Sugihara; Hiroo Masuda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)