A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier. - Masashi Horiguchi; Masakazu Aoki; Jun Etoh; Hitoshi Tanaka; Shin'ichi Ikenaga; Kiyoo Itoh 001; Kazuhiko Kajigaya; Hiroaki Kotani; Kazuyoshi Ohshima; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1990)

An experimental 1.5-V 64-Mb DRAM. - Yoshinobu Nakagome; Hitoshi Tanaka; Kan Takeuchi; Eiji Kume; Yasushi Watanabe; Toru Kaga; Yoshifumi Kawamoto; Fumio Murai; Ryuichi Izawa; Digh Hisamoto; Teruaki Kisu; Takashi Nishida; et al. (IEEE J. Solid State Circuits, 1991)

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM. - Yoshinobu Nakagome; Kiyoo Itoh 001; Kan Takeuchi; Eiji Kume; Hitoshi Tanaka; Masanori Isoda; Tatsunori Musha; Toru Kaga; Teruaki Kisu; Takashi Nishida; Yoshifumi Kawamoto; Masakazu Aoki (IEEE J. Solid State Circuits, 1991)

Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs. - Hitoshi Tanaka; Yoshinobu Nakagome; Jun Etoh; Eiji Yamasaki; Masakazu Aoki; Kazuyuki Miyazawa (IEEE J. Solid State Circuits, 1994)

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. - Takeshi Sakata; Masashi Horiguchi; Tomonori Sekiguchi; Shigeki Ueda; Hitoshi Tanaka; Eiji Yamasaki; Yoshinobu Nakagome; Masakazu Aoki; Toru Kaga; Makoto Ohkura; Ryo Nagai; Fumio Murai; et al. (IEEE J. Solid State Circuits, 1995)

A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. - Takao Watanabe; Ryo Fujita; Kazumasa Yanagisawa; Hitoshi Tanaka; Kazushige Ayukawa; Mitsuru Soga; Yuji Tanaka; Yoshimitsu Sugie; Yoshinobu Nakagome (IEEE J. Solid State Circuits, 1997)

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. - Hitoshi Tanaka; Masakazu Aoki; Takeshi Sakata; Shin'ichiro Kimura; Narumi Sakashita; Hideto Hidaka; Tadashi Tachibana; Katsutaka Kimura (IEEE J. Solid State Circuits, 1999)

Visualization of large-scale internal seiche in Lake Inawashiro. - Hitoshi Tanaka; Yutaka Fujita; Hiroto Yamaji (J. Vis., 2003)

A concepts-of-sentences associative neural network. - Hitoshi Tanaka; Jingtao Huang; Masafumi Hagiwara (Syst. Comput. Jpn., 2003)

Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications. - Kouji Tsunoda; Akira Sato; Hiroko Tashiro; Toshiro Nakanishi; Hitoshi Tanaka (IEICE Trans. Electron., 2005)

An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme. - Hiroki Fujisawa; Shuichi Kubouchi; Koji Kuroki; Naohisa Nishioka; Yoshiro Riho; Hiromasa Noda; Isamu Fujii; Hideyuki Yoko; Ryuuji Takishita; Takahiro Ito; Hitoshi Tanaka; Masayuki Nakamura (ISSCC, 2006)

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme. - Hiroki Fujisawa; Shuichi Kubouchi; Koji Kuroki; Naohisa Nishioka; Yoshiro Riho; Hiromasa Noda; Isamu Fujii; Hideyuki Yoko; Ryuuji Takishita; Takahiro Ito; Hitoshi Tanaka; Masayuki Nakamura (IEEE J. Solid State Circuits, 2007)

Ultra-Low Voltage Nano-Scale Memories - Kiyoo Itoh 001; Masashi Horiguchi; Hitoshi Tanaka (Springer, 2007)

Estimating damage-mitigation level of collision-prevention support braking. - Keisuke Suzuki; Hitoshi Tanaka; Yoshiki Miichi; Masami Aga (Intelligent Vehicles Symposium, 2011)

Influence of Polymer Gate Dielectrics on p-Channel and n-Channel Formation of Fluorene-type Polymer Light-emitting Transistors. - Hirotake Kajii; Masato Ise; Hitoshi Tanaka; Takahiro Ohtomo; Yutaka Ohmori (IEICE Trans. Electron., 2015)

A remark on two generalized Orlicz-Morrey spaces. - Sadek Gala; Yoshihiro Sawano; Hitoshi Tanaka (J. Approx. Theory, 2015)

Advanced Machine Learning Techniques for Predicting Nha Trang Shorelines. - Cheng Yin; Le Thanh Binh; Duong Tran Anh; Son T. Mai; Anh Le; Van-Hau Nguyen; Van-Chien Nguyen; Nguyen Xuan Tinh; Hitoshi Tanaka; Nguyen Trung Viet; Long Dinh Nguyen; Trung Q. Duong (IEEE Access, 2021)

Using Hybrid Wavelet-Exponential Smoothing Approach for Streamflow Modeling. - Vahid Nourani; Hessam Najafi; Alireza Babaeian Amini; Hitoshi Tanaka (Complex., 2021)

Deep Learning-enabled Detection and Classification of Bacterial Colonies using a Thin Film Transistor (TFT) Image Sensor. - Yuzhu Li; Tairan Liu; Hatice Ceylan Koydemir; Hongda Wang; Keelan O'Riordan; Bijie Bai; Yuta Haga; Junji Kobashi; Hitoshi Tanaka; Takaya Tamaru; Kazunori Yamaguchi; Aydogan Ozcan (CoRR, 2022)

Automatic Generation of Tactile Graphics of Characters to Support Handwriting of Blind Individuals. - Shunnosuke Sonobe; Hitoshi Tanaka; Akio Fujiyoshi (ICCHP (1), 2024)