BIST-Aided Scan Test - A New Method for Test Cost Reduction. - Takahisa Hiraide; Kwame Osei Boateng; Hideaki Konishi; Koichi Itaya; Michiaki Emori; Hitoshi Yamanaka; Takashi Mochiyama (VTS, 2003)

Delay defect screening for a 2.16GHz SPARC64 microprocessor. - Noriyuki Ito; Akira Kanuma; Daisuke Maruyama; Hitoshi Yamanaka; Tsuyoshi Mochizuki; Osamu Sugawara; Chihiro Endoh; Masahiro Yanagida; Takeshi Kono; Yutaka Isoda; Kazunobu Adachi; Takahisa Hiraide; et al. (ASP-DAC, 2006)

Design Methodology for 2.4GHz Dual-Core Microprocessor. - Noriyuki Ito; Hiroaki Komatsu; Akira Kanuma; Akihiro Yoshitake; Yoshiyasu Tanamura; Hiroyuki Sugiyama; Ryoichi Yamashita; Ken-ichi Nabeya; Hironobu Yoshino; Hitoshi Yamanaka; Masahiro Yanagida; Yoshitomo Ozeki; et al. (ASP-DAC, 2007)