A heuristic procedure for ordering MOS arrays. - Hitoshi Yoshizawa; Hiroshi Kawanishi; K. Kani (DAC, 1975)

Automatic layout algorithms for function blocks of CMOS gate arrays. - Shigeo Noda; Hitoshi Yoshizawa; Etsuko Fukuda; Haruo Kato; Hiroshi Kawanishi; Takashi Fujii (DAC, 1985)

How sub-micron delay and timing issues will be solved? - Hitoshi Yoshizawa (ASP-DAC, 1995)