A 1MHz-bandwidth type-I ΔΣ fractional-N synthesizer for WiMAX applications. - Hiva Hedayati; Bertan Bakkaloglu; Waleed Khalil (ISSCC, 2009)

A 1 MHz Bandwidth, 6 GHz 0.18 µm CMOS Type-I ΔΣ Fractional-NSynthesizer for WiMAX Applications. - Hiva Hedayati; Waleed Khalil; Bertan Bakkaloglu (IEEE J. Solid State Circuits, 2009)

Correction to "A 1 MHz Bandwidth, 6 GHz 0.18 μ m CMOS Type-I Delta Sigma Fractional-N Synthesizer for WiMAX Applications" [Dec 09 3244-3252]. - Hiva Hedayati; Waleed Khalil; Bertan Bakkaloglu (IEEE J. Solid State Circuits, 2010)

A 3 GHz Wideband Σ Δ Fractional-N Synthesizer With Switched-RC Sample-and-Hold PFD. - Hiva Hedayati; Bertan Bakkaloglu (IEEE Trans. Very Large Scale Integr. Syst., 2012)

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS. - Parag Upadhyaya; Jafar Savoj; Fu-Tai An; Ade Bekele; Anup P. Jose; Bruce Xu; Zhaoyin Daniel Wu; Didem Turker; Hesam Amir Aslanzadeh; Hiva Hedayati; Jay Im; Siok-Wei Lim; et al. (ISSCC, 2015)

3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET. - Yohan Frans; Scott McLeod; Hiva Hedayati; Mohamed Elzeftawi; Jin Namkoong; Winson Lin; Jay Im; Parag Upadhyaya; Ken Chang (ISSCC, 2016)

A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. - Yohan Frans; Mohamed Elzeftawi; Hiva Hedayati; Jay Im; Vassili Kireev; Toan Pham; Jaewook Shin; Parag Upadhyaya; Lei Zhou; Santiago Asuncion; Chris Borrelli; Geoff Zhang; et al. (VLSI Circuits, 2016)

A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET. - Yohan Frans; Scott McLeod; Hiva Hedayati; Mohamed Elzeftawi; Jin Namkoong; Winson Lin; Jay Im; Parag Upadhyaya; Ken Chang (IEEE J. Solid State Circuits, 2016)

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET. - Yohan Frans; Jaewook Shin; Lei Zhou; Parag Upadhyaya; Jay Im; Vassili Kireev; Mohamed Elzeftawi; Hiva Hedayati; Toan Pham; Santiago Asuncion; Chris Borrelli; Geoff Zhang; et al. (IEEE J. Solid State Circuits, 2017)

Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver. - Shankarram Athreya; Hiva Hedayati; Shayan Kazemkhani; Yanfei Chen; Saurabh Vats; Michael D. Scott 002; Bart Zeydel; Peter Keller; Jian Wang; Bhaskarareddy Avula; Boris Murmann; Echere Iroaga (ESSCIRC, 2018)