A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL. - Ki-Won Lee; Joo-Hwan Cho; Byoung-Jin Choi; Geun-Il Lee; Ho-Don Jung; Woo-Young Lee; Ki-Chon Park; Yongsuk Joo; Jaehoon Cha; Young-Jung Choi; Patrick B. Moran; Jin-Hong Ahn (IEEE J. Solid State Circuits, 2007)