Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. - Ho Fai Ko; Nicola Nicolici (Asian Test Symposium, 2004)

Functional Illinois Scan Design at RTL. - Ho Fai Ko; Nicola Nicolici (ICCD, 2004)

Register-transfer level functional scan for hierarchical designs. - Ho Fai Ko; Qiang Xu 001; Nicola Nicolici (ASP-DAC, 2005)

RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. - Ho Fai Ko; Nicola Nicolici (ICCD, 2006)

Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. - Ho Fai Ko; Nicola Nicolici (DATE, 2008)

On Automated Trigger Event Generation in Post-Silicon Validation. - Ho Fai Ko; Nicola Nicolici (DATE, 2008)

A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. - Ho Fai Ko; Nicola Nicolici (ISQED, 2008)

Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs. - Ho Fai Ko; Adam B. Kinsman; Nicola Nicolici (ITC, 2008)

Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. - Ho Fai Ko; Nicola Nicolici (J. Electron. Test., 2008)

Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. - Ho Fai Ko; Nicola Nicolici (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. - Ho Fai Ko; Nicola Nicolici (ETS, 2009)

Design-for-debug for post-silicon validation: Can high-level descriptions help? - Nicola Nicolici; Ho Fai Ko (HLDVT, 2009)

Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. - Ho Fai Ko; Nicola Nicolici (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. - Ho Fai Ko; Nicola Nicolici (ETS, 2010)

Automated trace signals selection using the RTL descriptions. - Ho Fai Ko; Nicola Nicolici (ITC, 2010)

Design-for-Debug Architecture for Distributed Embedded Logic Analysis. - Ho Fai Ko; Adam B. Kinsman; Nicola Nicolici (IEEE Trans. Very Large Scale Integr. Syst., 2011)

In-system constrained-random stimuli generation for post-silicon validation. - Adam B. Kinsman; Ho Fai Ko; Nicola Nicolici (ITC, 2012)

Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging. - Ho Fai Ko; Nicola Nicolici (IEEE Trans. Computers, 2012)

Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation. - Adam B. Kinsman; Ho Fai Ko; Nicola Nicolici (DAC, 2013)