Analysis of time dependent dielectric breakdown in nanoscale CMOS circuits. - Ho Joon Lee; Kyung Ki Kim (ISOCC, 2011)

On-chip HBD sensor for nanoscale CMOS technology. - Ho Joon Lee; Yong-Bin Kim; Kyung Ki Kim (MWSCAS, 2012)

Low power Null Convention Logic circuit design based on DCVSL. - Ho Joon Lee; Yong-Bin Kim (MWSCAS, 2013)

An area efficient low power high speed S-Box implementation using power-gated PLA. - Ho Joon Lee; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2014)

Full custom implementation of a S-Box circuit architecture using power gated PLA structure. - Ho Joon Lee; Yong-Bin Kim; Kyung Ki Kim (MWSCAS, 2014)

A process tolerant semi-self impedance calibration method for LPDDR4 memory controller. - Ho Joon Lee; Yong-Bin Kim (MWSCAS, 2015)

Blind Source Separation for Myelin Water Fraction Mapping Using Multi-Echo Gradient Echo Imaging. - Jae Eun Song; Jaewook Shin; Hongpyo Lee; Ho Joon Lee; Won-Jin Moon; Dong-Hyun Kim 008 (IEEE Trans. Medical Imaging, 2020)