Design of Frequency Multiplier with Delay Locked Loop that is insensitive to PVT Variation and prescreen Harmonic Lock. - Ho Won Kim 004; Kang-Yoon Lee (ICUFN, 2021)

Design of Multiplying Delay Locked Loop that prevents Harmonic Lock and is insensitive to PVT Variation. - Ho Won Kim 004; Kang-Yoon Lee (ISOCC, 2021)

Dual Band Wide Range PLL for IoT Application. - Ho Won Kim 004; Hun Park; Kang-Yoon Lee (ISOCC, 2022)