Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization. - Hochang Jang; Taewhan Kim 001 (DAC, 2009)

Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. - Hochang Jang; Deokjin Joo; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)