Systematic generation of FPGA-based FFT implementations. - Hojin Kee; Newton Petersen; Jacob Kornerup; Shuvra S. Bhattacharyya (ICASSP, 2008)

Resource-efficient acceleration of 2-dimensional Fast Fourier Transform computations on FPGAs. - Hojin Kee; Shuvra S. Bhattacharyya; Newton Petersen; Jacob Kornerup (ICDSC, 2009)

FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques. - Hojin Kee; Shuvra S. Bhattacharyya; Ian C. Wong; Yong Rao (ICASSP, 2010)

Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs. - Hsiang-Huang Wu; Hojin Kee; Nimish Sane; William Plishker; Shuvra S. Bhattacharyya (International Symposium on Rapid System Prototyping, 2010)

Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs. - Hojin Kee; Shuvra S. Bhattacharyya; Jacob Kornerup (ICSAMOS, 2010)

Systematic Exploration of Trade-Offs between Application Throughput and Hardware Resource Requirements in DSP Systems. - Hojin Kee (2010)

Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs. - Nimish Sane; Hojin Kee; Gunasekaran S. Seetharaman; Shuvra S. Bhattacharyya (J. Signal Process. Syst., 2011)

Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware. - Hojin Kee; Chung-Ching Shen; Shuvra S. Bhattacharyya; Ian C. Wong; Yong Rao; Jacob Kornerup (J. Signal Process. Syst., 2012)

Rapid and high-level constraint-driven prototyping using lab VIEW FPGA. - Hojin Kee; Swapnil Mhaske; David Uliana; Adam Arnesen; Newton Petersen; Taylor L. Riché; Dustyn Blasig; Tai Ly (GlobalSIP, 2014)

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation. - Swapnil Mhaske; David Uliana; Hojin Kee; Tai Ly; Ahsan Aziz; Predrag Spasojevic (Sarnoff Symposium, 2015)

High-Throughput FPGA-Based QC-LDPC Decoder Architecture. - Swapnil Mhaske; Hojin Kee; Tai Ly; Ahsan Aziz; Predrag Spasojevic (VTC Fall, 2015)

A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R. - Swapnil Mhaske; David Uliana; Hojin Kee; Tai Ly; Ahsan Aziz; Predrag Spasojevic (CoRR, 2015)

FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis. - Swapnil Mhaske; Hojin Kee; Tai Ly; Predrag Spasojevic (Sarnoff Symposium, 2016)

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis. - Swapnil Mhaske; Hojin Kee; Tai Ly; Ahsan Aziz; Predrag Spasojevic (Int. J. Reconfigurable Comput., 2017)