3.3-V baseband Gm-C filters for wireless transceiver applications. - Jaeyoung Shin; Sunki Min; Soosun Kim; Joongho Choi; Soohyoung Lee; Hojin Park; Jaewhui Kim (ISCAS (1), 2003)

Design of a Digital Home Service Delivery and Management System for OSGi Framework. - Taein Hwang; Hojin Park; Jin-Wook Chung (APNOMS, 2007)

Personal Mobile A/V Control Point for Home-to-Home Media Streaming. - Taein Hwang; Hojin Park; Jinwook Chung (IEEE Trans. Consumer Electron., 2008)

Architecture of home gateway for device collaboration in extended home space. - Hojin Park; Ilwoo Lee; Taein Hwang; Nam Kim (IEEE Trans. Consumer Electron., 2008)

Interoperability model for devices over heterogeneous home networks. - Hojin Park; Moonok Choi; Euihyun Paik; Nam Kim (IEEE Trans. Consumer Electron., 2009)

A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS. - Jenlung Liu; Sehyung Jeon; Tae-Kwang Jang; Dohyung Kim; Jihyun F. Kim; Jaejin Park; Hojin Park (A-SSCC, 2011)

EAFR-based DLNA proxy for high-quality video distribution in extended home space. - Taein Hwang; Hojin Park; Euihyun Paik; Jinwook Chung (IEEE Trans. Consumer Electron., 2011)

A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications. - Jong-Phil Hong; Sung-Jin Kim; Jenlung Liu; Nan Xing; Tae-Kwang Jang; Jaejin Park; Jihyun F. Kim; Taeik Kim; Hojin Park (ISSCC, 2012)

An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS. - Pyoungwon Park; Jaejin Park; Hojin Park; SeongHwan Cho (ISSCC, 2012)

Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization. - Taehwan Kim 007; Do-Gyoon Song; Sangho Youn; Jaejin Park; Hojin Park; Jaeha Kim (ICCAD, 2013)

A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter. - Tae-Kwang Jang; Nan Xing; Frank Liu 003; Jungeun Shin; Hyungreal Ryu; Jihyun F. Kim; Taeik Kim; Jaejin Park; Hojin Park (ISSCC, 2013)

A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. - Wooseok Kim; Jaejin Park; Jihyun F. Kim; Taeik Kim; Hojin Park; Deog-Kyoon Jeong (ISSCC, 2013)

10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation. - Minyoung Song; Young-Ho Kwak; Sunghoon Ahn; Hojin Park; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 0.010mm2 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology. - Kangyeop Choo; Sung-Jin Kim; Wooseok Kim; Jihyun F. Kim; Taeik Kim; Hojin Park (CICC, 2014)

15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider. - Jenlung Liu; Tae-Kwang Jang; Yonghee Lee; Jungeun Shin; Seunghoon Lee; Taeik Kim; Jaejin Park; Hojin Park (ISSCC, 2014)

A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology. - Sung-Jin Kim; Taeik Kim; Hojin Park (VLSIC, 2014)

Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. - Wooseok Kim; Jaejin Park; Hojin Park; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2014)

A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS. - Joo-Myoung Kim; Jae-Seung Lee; Sun-a Kim; Taeik Kim; Hojin Park; Sang-Gug Lee 001 (CICC, 2015)

15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology. - Sung-Jin Kim; Wooseok Kim; Minyoung Song; Jihyun F. Kim; Taeik Kim; Hojin Park (ISSCC, 2015)

14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS. - Hyojun Kim; Jinwoo Sang; Hyunik Kim; Youngwoo Jo; Taeik Kim; Hojin Park; SeongHwan Cho (ISSCC, 2015)

14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology. - Minyoung Song; Taeik Kim; Jihyun F. Kim; Wooseok Kim; Sung-Jin Kim; Hojin Park (ISSCC, 2015)

A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS. - Yudong Zhang 006; Woogeun Rhee; Taeik Kim; Hojin Park; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS. - Hyunik Kim; Yongjo Kim; Taeik Kim; Hojin Park; SeongHwan Cho (ISSCC, 2016)

A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. - Gyu-Seob Jeong; Wooseok Kim; Jaejin Park; Taeik Kim; Hojin Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Parallax: Automatic Data-Parallel Training of Deep Neural Networks. - Soojeong Kim; Gyeong-In Yu; Hojin Park; Sungwoo Cho; Eunji Jeong; Hyeonmin Ha; Sanha Lee; Joo Seong Jeong; Byung-Gon Chun (CoRR, 2018)

Parallax: Sparsity-aware Data Parallel Training of Deep Neural Networks. - Soojeong Kim; Gyeong-In Yu; Hojin Park; Sungwoo Cho; Eunji Jeong; Hyeonmin Ha; Sanha Lee; Joo Seong Jeong; Byung-Gon Chun (EuroSys, 2019)

Automating System Configuration of Distributed Machine Learning. - Woo-Yeon Lee; Markus Weimer; Brian Cho; Byung-Gon Chun; Yunseong Lee; Joo Seong Jeong; Gyeong-In Yu; Jooyeon Kim; Hojin Park; Beomyeol Jeon; Won Wook Song; Gunhee Kim (ICDCS, 2019)

More IOPS for Less: Exploiting Burstable Storage in Public Clouds. - Hojin Park; Gregory R. Ganger; George Amvrosiadis (HotCloud, 2020)

An Asynchronous Boost Converter With Time-Based Dual-Mode Control for Wide Load Range and High Efficiency in SSD Applications. - Kyoungjin Lee; Haneul Kim; Jehyung Yoon; Hyoung-Seok Oh; Jin-Hong Park; Byeong-Ha Park; Hojin Park; Yoonmyung Lee (IEEE Trans. Ind. Electron., 2020)

Open-Set Face Identification on Few-Shot Gallery by Fine-Tuning. - Hojin Park; Jaewoo Park; Andrew Beng Jin Teoh (ICPR, 2022)

Understanding Open-Set Recognition by Jacobian Norm of Representation. - Jaewoo Park; Hojin Park; Eunju Jeong; Andrew Beng Jin Teoh (CoRR, 2022)

Towards Query Efficient and Generalizable Black-Box Face Reconstruction Attack. - Hojin Park; Jaewoo Park; Xingbo Dong; Andrew Beng Jin Teoh (ICIP, 2023)

Pretrained Implicit-Ensemble Transformer for Open-Set Authentication on Multimodal Mobile Biometrics. - Jaeho Yoon; Jaewoo Park; Kensuke Wagata; Hojin Park; Andrew Beng Jin Teoh (ACM Multimedia, 2023)

Minimum Assumption Reconstruction Attacks: Rise of Security and Privacy Threats Against Face Recognition. - Dezhi Li; Hojin Park; Xingbo Dong; Yen-Lung Lai; Hui Zhang 039; Andrew Beng Jin Teoh; Zhe Jin (PRCV (5), 2023)

Mimir: Finding Cost-efficient Storage Configurations in the Public Cloud. - Hojin Park; Gregory R. Ganger; George Amvrosiadis (SYSTOR, 2023)

Face Reconstruction Transfer Attack as Out-of-Distribution Generalization. - Yoon Gyo Jung; Jaewoo Park; Xingbo Dong; Hojin Park; Andrew Beng Jin Teoh; Octavia I. Camps (ECCV (75), 2024)

Reducing Cross-Cloud/Region Costs with the Auto-Configuring MACARON Cache. - Hojin Park; Ziyue Qiu; Gregory R. Ganger; George Amvrosiadis (SOSP, 2024)

Understanding open-set recognition by Jacobian norm and inter-class separation. - Jaewoo Park; Hojin Park; Eunju Jeong; Andrew Beng Jin Teoh (Pattern Recognit., 2024)